參數(shù)資料
型號(hào): AD7366BRUZ-5500RL7
廠商: Analog Devices Inc
文件頁(yè)數(shù): 14/28頁(yè)
文件大?。?/td> 0K
描述: IC ADC 12BIT DUAL BIPO 24-TSSOP
設(shè)計(jì)資源: Driving the AD7366/7 Bipolar SAR ADC in Low-Distortion DC-Coupled Appls (CN0042)
標(biāo)準(zhǔn)包裝: 500
系列: iCMOS®
位數(shù): 12
采樣率(每秒): 500k
數(shù)據(jù)接口: DSP,MICROWIRE?,QSPI?,串行,SPI?
轉(zhuǎn)換器數(shù)目: 2
功率耗散(最大): 88.8mW
電壓電源: 模擬和數(shù)字,雙 ±
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 24-TSSOP(0.173",4.40mm 寬)
供應(yīng)商設(shè)備封裝: 24-TSSOP
包裝: 帶卷 (TR)
輸入數(shù)目和類型: 4 個(gè)單端,單極;4 個(gè)單端,雙極
配用: EVAL-AD7366CBZ-ND - BOARD EVALUATION FOR AD7366
AD7366-5/AD7367-5
Rev. A | Page 21 of 28
SHUTDOWN MODE
Shutdown mode is intended for use in applications where slow
throughput rates are required. Shutdown mode is suited to
applications where a series of conversions performed at a
relatively high throughput rate are followed by a long period of
inactivity and, thus, shutdown. When the AD7366-5/AD7367-5
are in full power-down, all analog circuitry is powered down.
The falling edge of CNVST initiates the conversion. The BUSY
output subsequently goes high to indicate that the conversion is
in progress. Once the conversion is completed, the BUSY output
returns low. If the CNVST signal is at logic low when BUSY
goes low, the part enters shutdown at the end of the conversion
phase. While the part is in shutdown mode, the digital output
code from the last conversion on each ADC can still be read
from the DOUT pins. To read the DOUT data, CS must be brought
low as described in the
section. The DOUT pins
return to three-state once
CS is brought back to logic high.
To exit full power-down and to power up the AD7366-5/
AD7367-5, a rising edge of CNVST is required. After the
required power-up time has elapsed, CNVST may be brought
low again to initiate another conversion, as shown in Figure 24
POWER-UP TIMES
As described in the Shutdown Mode section, the AD7366-5/
AD7367-5 have one power-down mode. This section deals with
the power-up time required when coming out of this mode. It
should be noted that these power-up times apply with the
recommended capacitors in place on the DCAPA and DCAPB pins.
To power up from shutdown, CNVST must be brought high and
remain high for a minimum of 70 μs, as shown in
.
When power supplies are first applied to the AD7366-5/AD7367-5,
the ADC can power up with CNVST in either the low or high
logic state. Before attempting a valid conversion, CNVST must
be brought high and remain high for the recommended power-
up time of 70 μs. CNVST can then be brought low to initiate a
conversion. With the AD7366-5/AD7367-5, no dummy conversion
is required before valid data can be read from the
DOUT pins.
If it is intended to place the part in shutdown mode when the
supplies are first applied, the AD7366-5/AD7367-5 must be
powered up, and a conversion initiated. However, CNVST
should remain in the logic low state, and when the BUSY signal
goes low, the part enters shutdown.
Once supplies are applied to the AD7366-5/AD7367-5, sufficient
time must be allowed for any external reference to power up
and to charge the various reference buffer decoupling capacitors
to their final values.
BUSY
SCLK
SERIAL READ OPERATION
CS
1
12
tCONVERT
t3
t2
ENTERS SHUTDOWN
tPOWER-UP
CNVST
06
84
2-
0
26
Figure 24. Autoshutdown Mode for AD7366-5
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