參數(shù)資料
型號(hào)： AD73360ASU
廠商： ANALOG DEVICES INC
元件分類(lèi)： 通信及網(wǎng)絡(luò)
英文描述： Six-Input Channel Analog Front End
中文描述： SPECIALTY TELECOM CIRCUIT, PQFP44
封裝： TQFP-44
文件頁(yè)數(shù)： 17/35頁(yè)
文件大?。?/td> 281K
代理商： AD73360ASU
REV. A
AD73360
–
17
–
Table XIII. Control Register G Description
7
6
5
4
3
2
1
0
SEEN
RMOD
CH6
CH5
CH4
CH3
CH2
CH1
Bit Name
Description
0
1
2
3
4
5
6
7
CH1
CH2
CH3
CH4
CH5
CH6
RMOD
SEEN
Channel 1 Select
Channel 2 Select
Channel 3 Select
Channel 4 Select
Channel 5 Select
Channel 6 Select
Reset Analog Modulator
Enable Single-Ended Input Mode
Table XIV. Control Register H Description
7
6
5
4
3
2
1
0
INV
TME
CH6
CH5
CH4
CH3
CH2
CH1
Bit Name
Description
0
1
2
3
4
5
6
7
CH1
CH2
CH3
CH4
CH5
CH6
TME
INV
Channel 1 Select
Channel 2 Select
Channel 3 Select
Channel 4 Select
Channel 5 Select
Channel 6 Select
Test Mode Enable
Enable Invert Channel Mode
CONTROL REGISTER G
CONTROL REGISTER H
REGISTER BIT DESCRIPTIONS
Control Register A
CRA:0
Data/Program Mode. This bit controls the operating mode of the AD73360. If CRA:1 is 0, then a 0 in this bit
places the part in Program Mode. If CRA:1 is 0, then a 1 in this bit places the part in Data Mode.
Mixed Mode. If this bit is a 0, then the operating mode is determined by CRA:0. If this bit is a 1, then the
part operates in Mixed Mode.
Reserved. This bit is reserved and should be programmed to 0 to ensure correct operation.
SPORT Loop Back. This is a diagnostic mode. This bit should be set to 0 to ensure correct operation.
Device Count Bits. These bits tell the AD73360 how many devices are used in a cascade. All devices in the
cascade should be programmed to the same value ensure correct operation. See Table XVIII.
Reset. Writing a 1 to this bit will initiate a software reset of the AD73360.
Control Register B
CRB:0
–
1
Decimation Rate. These bits are used to set the decimation of the AD73360. See Table VII.
CRB:2
–
3
Serial Clock Divider. These bits are used to set the serial clock frequency. See Table VI.
CRB:4
–
6
Master Clock Divider. These bits are used to set the Master Clock Divider ratio. See Table V.
CRB:7
Control Echo Enable. Setting this bit to a 1 will cause the AD73360 to write out any control words it receives.
This is used as a diagnostic mode. This bit should be set to 0 for correct operation in Mixed Mode or Data Mode.
CRA:1
CRA:2
CRA:3
CRA:4
–
6
CRA:7
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