參數(shù)資料
型號: AD73360AR
廠商: ANALOG DEVICES INC
元件分類: 通信及網(wǎng)絡(luò)
英文描述: Six-Input Channel Analog Front End
中文描述: SPECIALTY TELECOM CIRCUIT, PDSO28
封裝: SOIC-28
文件頁數(shù): 3/35頁
文件大小: 281K
代理商: AD73360AR
REV. A
–3–
AD73360
AD73360A
Typ
Parameter
Min
Max
Unit
Test Conditions/Comments
LOGIC INPUTS
V
INH
, Input High Voltage
V
INL
, Input Low Voltage
I
IH
, Input Current
C
IN
, Input Capacitance
LOGIC OUTPUTS
V
OH
, Output High Voltage
V
OL
, Output Low Voltage
Three-State Leakage Current
POWER SUPPLIES
AVDD1, AVDD2
DVDD
I
DD8
V
DD
0.8
0
V
DD
0.8
10
10
V
V
μ
A
pF
V
DD
0.4
0
10
V
DD
0.4
+10
V
V
μ
A
|IOUT|
100
μ
A
|IOUT|
100
μ
A
2.7
2.7
3.3
3.3
V
V
See Table I
NOTES
1
Operating temperature range is as follows:
40
°
C to +85
°
C. Therefore, T
MIN
=
40
°
C and T
MAX
= +85
°
C.
2
Test conditions: Input PGA set for 0 dB gain (unless otherwise noted).
3
At input to sigma-delta modulator of ADC.
4
Guaranteed by design.
5
Overall group delay will be affected by the sample rate and the external digital filtering.
6
The ADC
s input impedance is inversely proportional to DMCLK and is approximated by: (4
×
10
11
)/DMCLK.
7
Frequency response of ADC measured with input at audio reference level (the input level that produces an output level of
10 dBm0), with 38 dB preamplifier
bypassed and input gain of 0 dB.
8
Test Conditions: no load on digital inputs, analog inputs ac coupled to ground.
Specifications subject to change without notice.
Table I. Current Summary (AVDD = DVDD = 3.3 V)
Total
Current
(Max)
Analog
Current
Digital
Current
MCLK
ON
Conditions
SE
Comments
ADCs Only On
REFCAP Only On
REFCAP and
REFOUT Only On
All Sections Off
All Sections Off
12
0.75
10
0.04
26.5
1.0
1
0
YES
NO
REFOUT Disabled
REFOUT Disabled
3.3
0.01
0.01
0.04
1.2
0.03
4.5
1.5
0.1
0
0
0
NO
YES
NO
MCLK Active Levels Equal to 0 V and DVDD
Digital Inputs Static and Equal to 0 V or DVDD
The above values are in mA and are typical values unless otherwise noted. MCLK = 16.384 MHz; SCLK = 16.384 MHz.
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