±16.5V VDD/V
參數(shù)資料
型號(hào): AD7328BRUZ
廠商: Analog Devices Inc
文件頁數(shù): 13/37頁
文件大?。?/td> 0K
描述: IC ADC 12BIT+ SAR 8CHAN 20TSSOP
設(shè)計(jì)資源: Using AD7328 in Appls with Single-Ended Industrial-Level Signals (CN0047)
標(biāo)準(zhǔn)包裝: 75
系列: iCMOS®
位數(shù): 12
采樣率(每秒): 1M
數(shù)據(jù)接口: DSP,MICROWIRE?,QSPI?,串行,SPI?
轉(zhuǎn)換器數(shù)目: 1
功率耗散(最大): 30mW
電壓電源: 雙 ±
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 20-TSSOP(0.173",4.40mm 寬)
供應(yīng)商設(shè)備封裝: 20-TSSOP
包裝: 管件
輸入數(shù)目和類型: 8 個(gè)單端,單極;8 個(gè)單端,雙極;4 個(gè)差分,單極;4 個(gè)差分,雙極
產(chǎn)品目錄頁面: 777 (CN2011-ZH PDF)
Data Sheet
AD7328
Rev. C | Page 19 of 36
0
4852-
0
45
±16.5V VDD/VSS
±12V VDD/VSS
5
–6
V
CO
M
RANG
E
(
V
)
4
3
2
1
0
–1
–2
–3
–4
–5
VCC =3V
VREF =3V
±2.5V
RANGE
±10V
RANGE
±5V RANGE
±2.5V
RANGE
±5V RANGE
±10V
RANGE
Figure 35. Common-Mode Range for VCC = 3 V and REFIN/OUT = 3 V
04852-
046
±16.5V VDD/VSS
±12V VDD/VSS
V
CO
M
RANG
E
(
V
)
VCC =5V
VREF =3V
8
–4
6
4
2
0
–2
±2.5V
RANGE
±10V
RANGE
±5V RANGE
±2.5V
RANGE
±5V RANGE
±10V
RANGE
Figure 36. Common-Mode Range for VCC = 5 V and REFIN/OUT = 3 V
6
–8
4
2
0
–2
–4
–6
04852-
047
±16.5V VDD/VSS
±12V VDD/VSS
V
CO
M
RANG
E
(
V
)
VCC =3V
VREF =2.5V
±2.5V
RANGE
±10V
RANGE
±5V RANGE
±2.5V
RANGE
±5V RANGE
±10V
RANGE
Figure 37. Common-Mode Range for VCC = 3 V and REFIN/OUT = 2.5 V
8
–8
6
4
2
0
–2
–4
–6
04852-
048
±16.5V VDD/VSS
±12V VDD/VSS
V
CO
M
RANG
E
(
V
)
VCC =5V
VREF =2.5V
±2.5V
RANGE
±10V
RANGE
±5V RANGE
±2.5V
RANGE
±5V RANGE
±10V
RANGE
Figure 38. Common-Mode Range for VCC = 5 V and REFIN/OUT = 2.5 V
Pseudo Differential Inputs
The AD7328 can have four pseudo differential pairs or seven
pseudo differential inputs referenced to a common VIN pin. The
VIN+ inputs are coupled to the signal source and must have an
amplitude within the selected range for that channel as program-
med in the range register. A dc input is applied to the VIN pin.
The voltage applied to this input provides an offset for the
VIN+ input from ground or a pseudo ground. Pseudo differential
inputs separate the analog input signal ground from the ADC
ground, allowing cancellation of dc common-mode voltages.
Figure 39 shows the configuration of the AD7328 in pseudo
differential mode.
When a conversion takes place, the pseudo differential ground
corresponds to Code 4096, and the maximum amplitude
corresponds to Code +4095.
AD73281
VIN+
V+
V–
VDD
VSS
VCC
5V
1ADDITIONAL PINS OMITTED FOR CLARITY.
VIN
0
4852-
02
8
Figure 39. Pseudo Differential Inputs
Figure 40 and Figure 41 show the typical voltage range on the
VIN pin for various analog input ranges when configured in
the pseudo differential mode.
For example, when the AD7328 is configured to operate in
pseudo differential mode and the ±5 V range is selected with
±16.5 V VDD/VSS supplies and 5 V VCC, the voltage on the
VIN pin can vary from 6.5 V to +6.5 V.
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