AVCC = 4.75 V to 5.25 V," />
參數(shù)資料
型號： AD7264BSTZ-5-RL7
廠商： Analog Devices Inc
文件頁數(shù)： 27/29頁
文件大小： 0K
描述： IC ADC 14BIT 2CH 500KSPS 48LQFP
標(biāo)準(zhǔn)包裝： 500
位數(shù)： 14
采樣率（每秒）： 500k
數(shù)據(jù)接口： DSP，MICROWIRE?，QSPI?，串行，SPI?
轉(zhuǎn)換器數(shù)目： 2
功率耗散（最大）： 175mW
電壓電源： 單電源
工作溫度： -40°C ~ 105°C
安裝類型： 表面貼裝
封裝/外殼： 48-LQFP
供應(yīng)商設(shè)備封裝： 48-LQFP（7x7）
包裝： 帶卷 (TR)
輸入數(shù)目和類型： *
AD7264
Data Sheet
Rev. B | Page 6 of 28
TIMING SPECIFICATIONS
AVCC = 4.75 V to 5.25 V, CA_CBVCC = CC_CDVCC = 2.7 V to 5.25 V, VREF = 2.5 V internal/external; TA = TMIN to TMAX, unless otherwise noted.1
Table 2.
Limit at T
MIN, TMAX
Parameter
2.7 V ≤ V
DRIVE ≤ 3.6 V
4.75 V ≤ V
DRIVE ≤ 5.25 V
Unit
Description
f
SCLK
200
kHz min
34
342
MHz max
AD7264
20
MHz max
AD7264-5
t
CONVERT
19 × t
SCLK
19 × t
SCLK
ns max
t
SCLK = 1/fSCLK
560
ns max
AD7264
950
ns max
AD7264-5
t
QUIET
13
ns min
Minimum time between end of serial read/bus relinquish
and next falling edge of CS
t
2
10
ns min
CS to SCLK setup time
t
3
15
ns max
Delay from 19th SCLK falling edge until D
OUTA and DOUTB are
three-state disabled
t
4
29
23
ns max
Data access time after SCLK falling edge
t
5
15
13
ns min
SCLK to data valid hold time
t
6
0.4 × t
SCLK
0.4 × t
SCLK
ns min
SCLK high pulse width
t
7
0.4 × t
SCLK
0.4 × t
SCLK
ns min
SCLK low pulse width
t
8
13
ns min
CS rising edge to falling edge pulse width
t
9
13
ns max
CS rising edge to DOUTA, DOUTB high impedance/bus
relinquish
t
10
5
ns min
SCLK falling edge to D
OUTA, DOUTB high impedance
35
ns max
SCLK falling edge to D
OUTA, DOUTB high impedance
t
11
2
μs min
Minimum CAL pin high time
t
12
2
μs min
Minimum time between the CAL pin high and the CS
falling edge
t
13
3
ns min
D
IN setup time prior to SCLK falling edge
t
14
3
ns min
D
IN hold time after SCLK falling edge
t
POWER-UP
240
μs max
Internal reference, with a 1 μF decoupling capacitor
15
μs max
With an external reference, 10 μs typical
1 Sample tested during initial release to ensure compliance. All input signals are specified with t
R = tF = 5 ns (10% to 90% of VDD) and timed from a voltage level of 1.6 V.
All timing specifications given are with a 25 pF load capacitance. With a load capacitance greater than this value, a digital buffer or latch must be used. See the
2 The AD7264 is functional with a 40 MHz SCLK at 25°C, but specified performance is not guaranteed with SCLK frequencies greater than 34 MHz.
3 The time required for the output to cross 0.4 V or 2.4 V.
CS
SCLK
1
5
19
DOUTA
THREE-STATE
t4
2
3
4
20
t5
THREE-
STATE
t7
t3
18
DB11A
DB12A
DB13A
21
31
32
33
DB1A
DB0A
DOUTB
THREE-STATE
THREE-
STATE
DB11B
DB12B
DB13B
DB1B
DB0B
06732-
002
t2
t9
t8
tQUIET
t6
Figure 2. Serial Interface Timing Diagram
相關(guān)PDF資料
PDF描述
D38999/26WJ29PNLC CONN HSG PLUG 29POS STRGHT PINS
LTC1408CUH-12#PBF IC ADC 12BIT 600KSPS 32-QFN
D38999/26WJ29AN CONN HSG PLUG 29POS STRGHT PINS
LTC1854CG#TRPBF IC ADC 12BIT 8CH 100KSPS 28SSOP
VI-BNF-IX-B1 CONVERTER MOD DC/DC 72V 75W
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AD7264BSTZ-RL7 功能描述:IC ADC 14BIT 2CH 1MSPS 48LQFP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:- 位數(shù):16 采樣率（每秒）:45k 數(shù)據(jù)接口:串行 轉(zhuǎn)換器數(shù)目:2 功率耗散（最大）:315mW 電壓電源:模擬和數(shù)字 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:28-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:28-SOIC W 包裝:帶卷 (TR) 輸入數(shù)目和類型:2 個單端，單極
AD7265 制造商:AD 制造商全稱:Analog Devices 功能描述:Differential Input, Dual 1 MSPS, 12-Bit, 3-Channel SAR ADC
AD7265ACP 制造商:Analog Devices 功能描述:
AD7265ASU 制造商:Analog Devices 功能描述:
AD7265BCP 制造商:Analog Devices 功能描述:ADC Dual SAR 1Msps 12-bit Serial 32-Pin LFCSP EP
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺，查看報價

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺，查看報價

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*