AVCC = 4.75 V to 5.25 V, C
參數(shù)資料
型號: AD7262BSTZ-RL7
廠商: Analog Devices Inc
文件頁數(shù): 28/33頁
文件大小: 0K
描述: IC ADC 12BIT W/PGA&COM 48-LQFP
標(biāo)準(zhǔn)包裝: 1
位數(shù): 12
采樣率(每秒): 1M
數(shù)據(jù)接口: DSP,MICROWIRE?,QSPI?,串行,SPI?
轉(zhuǎn)換器數(shù)目: 2
功率耗散(最大): 120mW
電壓電源: 單電源
工作溫度: -40°C ~ 105°C
安裝類型: 表面貼裝
封裝/外殼: 48-LQFP
供應(yīng)商設(shè)備封裝: 48-LQFP(7x7)
包裝: 標(biāo)準(zhǔn)包裝
輸入數(shù)目和類型: 2 個差分,單極
產(chǎn)品目錄頁面: 777 (CN2011-ZH PDF)
其它名稱: AD7262BSTZ-RL7DKR
AD7262
Rev. 0 | Page 3 of 32
SPECIFICATIONS
AVCC = 4.75 V to 5.25 V, CA_CBVCC = CC_CDVCC = 2.7 V to 5.25 V, VDRIVE = 2.7 V to 5.25 V, fSAMPLE = 1 MSPS and fSCLK = 40 MHz
for AD7262, fSAMPLE = 500 kSPS and fSCLK = 20 MHz for AD7262-5, VREF = 2.5 V internal/external; TA = 40°C to +105°C, unless
otherwise noted.
Table 1.
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
DYNAMIC PERFORMANCE1
fIN = 100 kHz sine wave
Signal-to-Noise Ratio (SNR)2
70
73
dB
PGA gain setting = 2
Signal-to-(Noise + Distortion) Ratio
70
72
dB
Total Harmonic Distortion (THD)2
85
77
dB
Spurious-Free Dynamic Range (SFDR)2
97
dB
Common-Mode Rejection Ratio (CMRR)3
76
dB
For PGA gain setting = 2, ripple
frequency of 50 Hz/60 Hz; see Figure 17
ADC-to-ADC Isolation3
90
dB
1.2
MHz
@ 3 dB; PGA gain setting = 128
1.7
MHz
@ 3 dB; PGA gain setting = 2
DC ACCURACY
Resolution
12
Bits
Integral Nonlinearity2
±0.5
±1
LSB
Differential Nonlinearity2
±0.5
±0.99
LSB
Guaranteed no missed codes to 12 bits
Positive Full-Scale Error2
±0.122
±0.305
% FSR
Pregain calibration
±0.018
% FSR
Postgain calibration
Positive Full-Scale Error Match
±0.061
% FSR
Zero Code Error2
±0.092
±0.244
% FSR
Preoffset and pregain calibration
±0.012
% FSR
Postoffset and postgain calibration
Zero Code Error Match
±0.061
% FSR
Negative Full-Scale Error2
±0.122
±0.305
% FSR
Pregain calibration
±0.018
% FSR
Postgain calibration
Negative Full-Scale Error Match
±0.061
% FSR
Zero Code Error Drift
2.5
μV/°C
ANALOG INPUT
Input Voltage Range, VIN+ and VIN
Gain
2
V
REF
CM
×
±
V
VCM = AVCC/2; PGA gain setting ≥ 2
Common-Mode Voltage Range, VCM
VCM 100 mV
VCM + 100 mV
V
VCM = 2; PGA gain setting = 1;
(VCC/2) 0.4
(VCC/2) + 0.2
V
VCM = AVCC/2; PGA gain setting = 2
(VCC/2) 0.4
(VCC/2) + 0.4
V
VCM = AVCC/2; 3 ≤ PGA gain setting ≤ 32
(VCC/2) 0.6
(VCC/2) + 0.8
V
VCM = AVCC/2; PGA gain setting ≥ 48
DC Leakage Current
±0.001
±1
μA
Input Capacitance3
5
pF
Input Impedance3
1
REFERENCE INPUT/OUTPUT
Reference Output Voltage5
2.495
2.5
2.505
V
2.5 V ± 5 mV max @ 25°C
Reference Input Voltage Range
2.5
V
DC Leakage Current
±0.3
±1
μA
External reference applied to
Pin VREFA/Pin VREFB
Input Capacitance3
20
pF
VREFA, VREFB Output Impedance3
4
Ω
Reference Temperature Coefficient
20
ppm/°C
VREF Noise3
20
μV rms
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