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參數資料
| 型號： | AD7262BSTZ-RL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數： | 19/33頁 |
| 文件大小： | 0K |
| 描述： | IC ADC 12BIT W/PGA&COM 48-LQFP |
| 標準包裝： | 1 |
| 位數： | 12 |
| 采樣率（每秒）： | 1M |
| 數據接口： | DSP，MICROWIRE?，QSPI?，串行，SPI? |
| 轉換器數目： | 2 |
| 功率耗散（最大）： | 120mW |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 105°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-LQFP |
| 供應商設備封裝： | 48-LQFP（7x7） |
| 包裝： | 標準包裝 |
| 輸入數目和類型： | 2 個差分，單極 |
| 產品目錄頁面： | 777 (CN2011-ZH PDF) |
| 其它名稱： | AD7262BSTZ-RL7DKR |
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AD7262
Rev. 0 | Page 25 of 32
SERIAL INTERFACE
the serial interfacing of the AD7262/AD7262-5. The serial clock
provides the conversion clock and controls the transfer of
information from the AD7262/AD7262-5 after the conversion.
The AD7262/AD7262-5 has two output pins corresponding to
each ADC. Data can be read from the AD7262/AD7262-5 using
both DOUTA and DOUTB. Alternatively, a single output pin of the
user’s choice can be used. The SCLK input signal provides the
clock source for the serial interface.
The falling edge of CS puts the track-and-hold into hold mode,
at which point the analog input is sampled. The conversion is
also initiated at this point and requires a minimum of 19 SCLKs
to complete. The DOUTx lines remain in three-state while the
conversion is taking place. On the 19th SCLK falling edge, the
AD7262/AD7262-5 return to track mode and the DOUTA and
DOUTB lines are enabled. The data stream consists of 12 bits of
data, MSB first.
The MSB of the conversion result is clocked out on the 19th
SCLK falling edge to be read by the microcontroller or DSP on
either the subsequent SCLK falling edge (20th falling edge) or
the 20th SCLK rising edge. The choice of whether to read on the
rising or falling SCLK edge depends on the SCLK frequency
being used. When the maximum SCLK frequency of 40 MHz is
used with a VDRIVE voltage of 5 V, the maximum specified access
time (t4) is 23 ns, resulting in 2 ns of setup time, which may not
be sufficient for most DSPs or microcontrollers. Under these
conditions, it is recommended to use the rising SCLK edge to
read the data. In this case, the MSB of the conversion result is
clocked out on the 19th SCLK falling edge to be read on the 20th
SCLK rising edge, as shown in Figure 33. The remaining data is
then clocked out by subsequent SCLK falling edges. When using
a 40 MHz SCLK frequency, the 20th falling clock edge on the
serial clock clocks out the second data bit, which is provided for
reading on the 21st SCLK rising edge. The remainder of the 12-bit
result follows, with the final bit in the data transfer being valid
on the 31st rising edge. The LSB is provided on the 30th falling
clock edge.
An alternative to reading on the rising SCLK edge is to use a
slower SCLK frequency. If a slower SCLK frequency is used, for
example 32 MHz with the AD7262, this will enable reading on
the subsequent falling SCLK edge after the data has been
clocked out, as illustrated in Figure 35. A throughput rate of
1 MSPS can still be achieved for the AD7262 when a 32 MHz
SCLK frequency is used. The remaining data is then clocked out
by subsequent SCLK falling edges. When using a 32 MHz or
less SCLK frequency with the AD7262 or when using the
AD7262-5, the 20th falling clock edge on the serial clock has the
MSB provided for reading and also clocks out the second data bit.
The remainder of the 12-bit result follows, with the final bit in
the data transfer being valid on the 31st falling edge. The LSB is
provided on the 30th falling clock edge.
On the rising edge of CS, DOUTA and DOUTB go back into three-
state. If CS is not brought high after 31 SCLKs but is instead
held low for an additional 12 SCLK cycles, the data from
ADC B is output on DOUTA after the ADC A result. Likewise,
the data from ADC A is output on DOUTB after the ADC B
result. This is illustrated in
example. In this case, the DOUT line in use goes back into three-
state on the 45th SCLK falling edge or the rising edge of
CS,
whichever occurs first.
If the falling edge of SCLK coincides with the falling edge of CS,
the falling edge of SCLK is not acknowledged by the AD7262
and the next falling edge of SCLK is the first one registered after
the falling edge of CS.
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