參數(shù)資料
型號(hào)： AD725ARZ-RL
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 15/20頁(yè)
文件大?。?/td> 0K
描述： IC ENCODER RGB TO NTSC 16-SOIC
標(biāo)準(zhǔn)包裝： 1,000
類型： 視頻編碼器
應(yīng)用： RGB 至 NTSC/PAL
電壓 - 電源，數(shù)字： 4.75 V ~ 5.25 V
安裝類型： 表面貼裝
封裝/外殼： 16-SOIC（0.295"，7.50mm 寬）
供應(yīng)商設(shè)備封裝： 16-SOIC W
包裝： 帶卷 (TR)
REV. 0
–4–
AD725
PIN DESCRIPTIONS
Pin
Mnemonic
Description
Equivalent Circuit
1
STND
Encoding Standard Pin. A Logic HIGH input selects NTSC encoding.
Circuit A
A Logic LOW input selects PAL encoding.
TTL Logic Levels.
2
AGND
Analog Ground Connection.
3
4FSC
4FSC Clock Input.
Circuit A
For NTSC: 14.318 180 MHz.
For PAL: 17.734 475 MHz.
TTL Logic Levels.
4
APOS
Analog Positive Supply (+5 V
± 5%).
5
CE
Chip Enable. A Logic HIGH input enables the encode function.
Circuit A
A Logic LOW input powers down chip when not in use.
TTL Logic Levels.
6
RIN
Red Component Video Input.
Circuit B
0 mV to 714 mV AC-Coupled.
7
GIN
Green Component Video Input.
Circuit B
0 mV to 714 mV AC-Coupled.
8
BIN
Blue Component Video Input.
Circuit B
0 mV to 714 mV AC-Coupled.
9
CRMA
Chrominance Output.*
Circuit C
Approximately 1.8 V peak-to-peak for both NTSC and PAL.
10
COMP
Composite Video Output.*
Circuit C
Approximately 2.5 V peak-to-peak for both NTSC and PAL.
11
LUMA
Luminance plus CSYNC Output.*
Circuit C
Approximately 2 V peak-to-peak for both NTSC and PAL.
12
YTRAP
Luminance Trap Filter Tap. Attach L-C resonant network to reduce cross-color artifacts.
Circuit D
13
DGND
Digital Ground Connection.
14
DPOS
Digital Positive Supply (+5 V
± 5%).
15
VSYNC
Vertical Sync Signal (if using external CSYNC set at > +2 V). TTL Logic Levels.
Circuit A
16
HSYNC
Horizontal Sync Signal (or CSYNC signal). TTL Logic Levels.
Circuit A
*The Luminance, Chrominance and Composite Outputs are at twice normal levels for driving 75
reverse-terminated lines.
7
VCLAMP
6
8
DPOS
DGND
3
1
5
15
16
DPOS
DGND
10
9
11
APOS
AGND
DGND
DPOS
APOS
AGND
DGND
DPOS
12
1k
Circuit A
Circuit B
Circuit C
Circuit D
Figure 1. Equivalent Circuits
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