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參數(shù)資料
| 型號(hào)： | AD7243BRZ |
| 廠商： | Analog Devices Inc |
| 文件頁(yè)數(shù)： | 7/12頁(yè) |
| 文件大小： | 0K |
| 描述： | IC DAC 12BIT SRL LC2MOS 16SOIC |
| 產(chǎn)品培訓(xùn)模塊： | Data Converter Fundamentals DAC Architectures |
| 標(biāo)準(zhǔn)包裝： | 47 |
| 系列： | DACPORT® |
| 設(shè)置時(shí)間： | 10µs |
| 位數(shù)： | 12 |
| 數(shù)據(jù)接口： | 串行 |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 電壓電源： | 雙 ± |
| 功率耗散（最大）： | 100mW |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-SOIC（0.295"，7.50mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 16-SOIC W |
| 包裝： | 管件 |
| 輸出數(shù)目和類型： | 1 電壓，單極；1 電壓，雙極 |
| 采樣率（每秒）： | 300k |
AD7243
–4–
REV. A
AD7243 PIN FUNCTION DESCRIPTIONS (DIP and SOIC PIN NUMBERS)
Pin
Mnemonic
Description
1
REFIN
Voltage Reference Input. It is internally buffered before being applied to the DAC. The nominal reference
voltage for specified operation of the AD7243 is 5 V.
2
REFOUT
Voltage Reference Output. The internal 5 V analog reference is provided at this pin. To operate the part -
using its internal reference, REFOUT should be connected to REFIN.
3
CLR
Clear, Logic Input. Taking this input low sets VOUT to 0 V in both unipolar ranges and the two’s complement
bipolar range and to –REFIN in the offset binary bipolar range.
4
BIN/COMP
Logic Input. This input selects the data format to be either binary or two’s complement. In both unipolar
ranges, natural binary format is selected by connecting this input to a Logic “0.” In the bipolar configuration,
offset binary format is selected with a Logic “0” while a Logic “1” selects two’s complement format.
5
SCLK
Serial Clock, Logic Input. Data is clocked into the input register on each falling SCLK edge.
6
SDIN
Serial Data In, Logic Input. The 16-bit serial data word is applied to this input.
7
SYNC
Data Synchronization Pulse, Logic Input. Taking this input low initializes the internal logic in readiness for a
new data word.
8
DGND
Digital Ground. Ground reference for all digital circuitry.
9
LDAC
Load DAC, Logic Input. Updates the DAC output. The DAC output is updated on the falling edge of this
signal or alternatively if this line is permanently low, an automatic update mode is selected whereby the DAC
is updated on the 16th falling SCLK pulse.
10
DCEN
Daisy-Chain Enable, Logic Input. Connect this pin high if a daisy-chain interface is being used, otherwise
this pin must be connected low.
11
SDO
Serial Data Out, Logic Output. With DCEN at Logic “1” this output is enabled, and the serial data in the
input shift register is clocked out on each falling SCLK edge.
12
AGND
Analog Ground. Ground reference for all analog circuitry.
13
ROFS
Output Offset Resistor for the amplifier. It is connected to VOUT for the +5 V range, to AGND for the +10 V
range and to REFIN for the –5 V to +5 V range.
14
VOUT
Analog Output Voltage. This is the buffer amplifier output voltage. Three different output voltage ranges can
be chosen: 0 V to +5 V, 0 to +10 V and –5 V to +5 V.
15
VSS
Negative Power Supply (used for the output amplifier only, may be connected to 0 V for single supply
operation or to –12 V to –15 V for dual supplies).
16
VDD
Positive Power Supply (+12 V to +15 V).
TERMINOLOGY
Bipolar Zero Error
Bipolar Zero Error is the voltage measured at VOUT when the
DAC is configured for bipolar output and loaded with all 0s
(Two’s Complement Coding) or with 1000 0000 0000 (Offset
Binary Coding). It is due to a combination of offset errors in the
DAC, amplifier and mismatch between the internal gain resis-
tors around the amplifier.
Full-Scale Error
Full-Scale Error is a measure of the output error when the am-
plifier output is at full scale (for the bipolar output range full
scale is either positive or negative full scale). It is measured with
respect to the reference input voltage and includes the offset
errors.
Digital-to-Analog Glitch Impulse
This is the voltage spike that appears at VOUT when the digital
code in the DAC latch changes, before the output settles to its
final value. The energy in the glitch is specified in nV secs, and
is measured for an all codes change from 0000 0000 0000 to
1111 1111 1111 and vice versa.
Digital Feedthrough
This is a measure of the voltage spike that appears on VOUT as a
result of feedthrough from the digital inputs on the AD7243. It
is measured with
LDAC held high.
Relative Accuracy (Linearity)
Relative Accuracy, or endpoint linearity, is a measure of the
maximum deviation of the DAC transfer function from a
straight line passing through the endpoints of the transfer func-
tion. It is measured after allowing for zero and full-scale errors
and is expressed in LSBs or as a percentage of full-scale reading.
Single Supply Linearity and Gain Error
The output amplifier on the AD7243 can have true negative off-
sets even when the part is operated from a single +15 V supply.
However, because the negative supply rail (VSS) is 0 V, the out-
put cannot actually go negative. Instead, when the output offset
voltage is negative, the output voltage sits at 0 V, resulting in the
transfer function shown in Figure 1.
OUTPUT
VOLTAGE
NEGATIVE
OFFSET
DAC CODE
0V
{
Figure 1. Effect of Negative Offset (Single Supply)
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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| AD7243BRZ-REEL | 功能描述:IC SRL DAC 12BIT LC2MOS 16-SOIC RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器 系列:DACPORT® 標(biāo)準(zhǔn)包裝:47 系列:- 設(shè)置時(shí)間:2µs 位數(shù):14 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:1 電壓電源:單電源 功率耗散（最大）:55µW 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:28-SSOP（0.209"，5.30mm 寬） 供應(yīng)商設(shè)備封裝:28-SSOP 包裝:管件 輸出數(shù)目和類型:1 電流，單極；1 電流，雙極 采樣率（每秒）:* |
| AD7243SQ | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:STANDARD MICROCIRCUIT DRAWING |
| AD7243SQ/883B | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:12-Bit Digital-to-Analog Converter |
| AD7243SQ2 | 制造商:AD 制造商全稱:Analog Devices 功能描述:LC2MOS 12-Bit Serial DACPORT |
| AD7243SQ883B | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:STANDARD MICROCIRCUIT DRAWING |
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