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參數(shù)資料
| 型號(hào)： | AD7243BRZ |
| 廠商： | Analog Devices Inc |
| 文件頁(yè)數(shù)： | 3/12頁(yè) |
| 文件大小： | 0K |
| 描述： | IC DAC 12BIT SRL LC2MOS 16SOIC |
| 產(chǎn)品培訓(xùn)模塊： | Data Converter Fundamentals DAC Architectures |
| 標(biāo)準(zhǔn)包裝： | 47 |
| 系列： | DACPORT® |
| 設(shè)置時(shí)間： | 10µs |
| 位數(shù)： | 12 |
| 數(shù)據(jù)接口： | 串行 |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 電壓電源： | 雙 ± |
| 功率耗散（最大）： | 100mW |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-SOIC（0.295"，7.50mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 16-SOIC W |
| 包裝： | 管件 |
| 輸出數(shù)目和類型： | 1 電壓，單極；1 電壓，雙極 |
| 采樣率（每秒）： | 300k |
REV. A
–11–
AD7243
Common clock, data, and synchronization signals are applied to
all DACs in the chain. The loading sequence starts by taking
SYNC low. The data is then clocked into the input registers on
the falling edge of SCLK. Sixteen clock pulses are required for
each DAC in the chain. The data ripples through the input reg-
isters with the first 16-bit word filling the last register in the
chain after 16N clock pulses where N = the total number of
DACs in the chain.
When valid data has been loaded into all the registers, the
SYNC input should be taken high and a common LDAC pulse
used to update all the DACs simultaneously.
APPLICATIONS
OPTO-ISOLATED INTERFACE
In many process control type applications it is necessary to pro-
vide an isolation barrier between the controller and the unit be-
ing controlled. Opto-isolators can provide voltage isolation in
excess of 3 kV. The serial loading structure of the AD7243
makes it ideal for opto-isolated interfaces as the number of in-
terface lines is kept to a minimum.
Figure 17 shows a 4-channel isolated interface using the
AD7243. The DCEN pin must be connected high to enable the
daisy-chain facility. Four channels with 12-bit resolution are
provided in the circuit shown, but this may be expanded to ac-
commodate any number of DAC channels without any extra
isolation circuitry.
The sequence of events to program the output channels is as
follows:
1. Take the
SYNC line low.
2. Transmit the data as four 16-bit words. A total of 64 clock
pulses is required to clock the data through the chain.
3. Take the
SYNC line high.
4. Pulse the
LDAC line low. This updates all output channels
simultaneously on the falling edge of
LDAC.
To reduce the number of opto-couplers, the
LDAC line could
be driven from a one shot which is triggered by the rising edge
on the
SYNC line. A low level pulse of 50 ns duration or greater
is all that is required to update the outputs.
SCLK
AD7243*
SYNC
LDAC
SDIN
DCEN
SDO
SCLK
AD7243*
SYNC
LDAC
SDIN
DCEN
SDO
SCLK
AD7243*
SYNC
LDAC
SDIN
DCEN
SDO
SCLK
AD7243*
SYNC
LDAC
SDIN
DCEN
SDO
VOUT
*ADDITIONAL PINS OMITTED FOR CLARITY
DATA OUT
CLOCK OUT
SYNC OUT
CONTROL OUT
CONTROLLER
VDD
VOUT(A)
QUAD OPTO-COUPLER
VDD
VOUT(B)
VOUT(C)
VOUT(D)
VOUT
Figure 17. Four-Channel Opto-lsolated Interface
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD7243BRZ-REEL | 功能描述:IC SRL DAC 12BIT LC2MOS 16-SOIC RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器 系列:DACPORT® 標(biāo)準(zhǔn)包裝:47 系列:- 設(shè)置時(shí)間:2µs 位數(shù):14 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:1 電壓電源:單電源 功率耗散（最大）:55µW 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:28-SSOP（0.209"，5.30mm 寬） 供應(yīng)商設(shè)備封裝:28-SSOP 包裝:管件 輸出數(shù)目和類型:1 電流，單極；1 電流，雙極 采樣率（每秒）:* |
| AD7243SQ | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:STANDARD MICROCIRCUIT DRAWING |
| AD7243SQ/883B | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:12-Bit Digital-to-Analog Converter |
| AD7243SQ2 | 制造商:AD 制造商全稱:Analog Devices 功能描述:LC2MOS 12-Bit Serial DACPORT |
| AD7243SQ883B | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:STANDARD MICROCIRCUIT DRAWING |
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