參數(shù)資料
型號(hào)： AD7193BCPZ-RL7
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 17/57頁(yè)
文件大小： 0K
描述： IC ADC 24BIT SPI 4.8KHZ 32LFCSP
標(biāo)準(zhǔn)包裝： 1,500
位數(shù)： 24
采樣率（每秒）： 4.8k
數(shù)據(jù)接口： DSP，MICROWIRE?，QSPI?，串行，SPI?
轉(zhuǎn)換器數(shù)目： 1
電壓電源： 模擬和數(shù)字
工作溫度： -40°C ~ 105°C
安裝類型： 表面貼裝
封裝/外殼： 32-WFQFN 裸露焊盤，CSP
供應(yīng)商設(shè)備封裝： 32-LFCSP-WQ（5x5）
包裝： 帶卷 (TR)
輸入數(shù)目和類型： 4 個(gè)差分，單極；4 個(gè)差分，雙極；8 個(gè)偽差分，單極；8 個(gè)偽差分，雙極
Data Sheet
AD7193
Rev. D | Page 23 of 56
STATUS REGISTER
RS2, RS1, RS0 = 000; Power-On/Reset = 0x80
The status register is an 8-bit read-only register. To access the
ADC status register, the user must write to the communications
register, select the next operation to be a read operation, and
load Bit RS2, Bit RS1, and Bit RS0 with 0. Table 19 outlines the bit
designations for the status register. SR0 through SR7 indicate the
bit locations, SR denoting that the bits are in the status register.
SR7 denotes the first bit of the data stream. The number in paren-
theses indicates the power-on/reset default status of that bit.
SR7
SR6
SR5
SR4
SR3
SR2
SR1
SR0
RDY(1)
ERR(0)
NOREF(0)
Parity(0)
CHD3(0)
CHD2(0)
CHD1(0)
CHD0(0)
Table 19. Status Register (SR) Bit Designations
Bit
Location
Bit Name
Description
SR7
RDY
Ready bit for the ADC. This bit is cleared when data is written to the ADC data register. The RDY bit is set
automatically after the ADC data register is read, or a period of time before the data register is updated,
with a new conversion result to indicate to the user that the conversion data should not be read. It is also
set when the part is placed in power-down mode or idle mode or when SYNC is taken low. The end of a
conversion is also indicated by the DOUT/RDY pin. This pin can be used as an alternative to the status
register for monitoring the ADC for conversion data.
SR6
ERR
ADC error bit. This bit is written to at the same time as the RDY bit. This bit is set to indicate that the result
written to the ADC data register is clamped to all 0s or all 1s. Error sources include overrange, underrange,
or the absence of a reference voltage. This bit is cleared when the result written to the data register
returns to within the allowed analog input range. The ERR bit is also set during calibrations if the reference
source is invalid or if the applied analog input voltages are outside range during system calibrations.
SR5
NOREF
No external reference bit. This bit is set to indicate that the selected reference (REFIN1 or REFIN2) is at a
voltage that is below a specified threshold. When set, conversion results are clamped to all 1s. This bit is
cleared to indicate that a valid reference is applied to the selected reference pins. The NOREF bit is enabled by
setting the REFDET bit in the configuration register to 1.
SR4
Parity
Parity check of the data register. If the ENPAR bit in the mode register is set and there is an odd number of
1s in the data register, the parity bit is set. It is cleared if there is an even number of 1s in the data register.
The DAT_STA bit in the mode register should be set when the parity check is used. When the DAT_STA bit
is set, the contents of the status register are transmitted along with the data for each data register read.
SR3 to SR0
CHD3 to CHD0
These bits indicate which channel corresponds to the data register contents. They do not indicate which
channel is presently being converted but indicate which channel was selected when the conversion
contained in the data register was generated.
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