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參數(shù)資料
| 型號： | AD7171BCPZ-500RL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 4/16頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 16BIT SER 125HZ 10LFCSP |
| 標準包裝： | 1 |
| 位數(shù)： | 16 |
| 采樣率（每秒）： | 125 |
| 數(shù)據(jù)接口： | 串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 105°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 10-WFDFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 10-LFCSP-WD（3x3） |
| 包裝： | 標準包裝 |
| 輸入數(shù)目和類型： | 1 個差分，雙極 |
| 產(chǎn)品目錄頁面： | 777 (CN2011-ZH PDF) |
| 其它名稱： | AD7171BCPZ-500RL7DKR |
AD7171
Data Sheet
Rev. A | Page 12 of 16
GROUNDING AND LAYOUT
Because the analog input and reference input of the ADC are
differential, most of the voltages in the analog modulator are
common-mode voltages. The excellent common-mode reject-
ion of the part removes common-mode noise on these inputs.
The digital filter provides rejection of broadband noise on the
power supply, except at integer multiples of the modulator
sampling frequency. The digital filter also removes noise from
the analog and reference inputs provided that these noise
sources do not saturate the analog modulator. As a result, the
AD7171 is more immune to noise interference than conven-
tional high resolution converters. However, because the noise
levels from the AD7171 are so low, care must be taken with
regard to grounding and layout.
The printed circuit board that houses the AD7171 should be
designed such that the analog and digital sections are separated
and confined to certain areas of the board. A minimum etch
technique is generally best for ground planes because it gives
the best shielding.
It is recommended that the GND pin of the AD7171 be tied to
the analog ground (AGND) plane of the system. In any layout,
it is important that the user pay attention to the flow of currents
in the system, and ensure that the return paths for all currents
are as close as possible to the paths the currents took to reach
their destinations. Avoid forcing digital currents to flow through
the AGND sections of the layout.
The ground plane of the AD7171 should be allowed to run
under the AD7171 to prevent noise coupling. The power supply
lines to the AD7171 should use as wide a trace as possible to
provide low impedance paths and reduce the effects of glitches
on the power supply line. Fast switching signals such as clocks
should be shielded with digital ground to avoid radiating noise
to other sections of the board, and clock signals should never be
run near the analog inputs. Avoid crossover of digital and
analog signals. Traces on opposite sides of the board should run
at right angles to each other. This reduces the effects of feedthrough
through the board. A microstrip technique is by far the best, but
it is not always possible with a double-sided board. In this
technique, the component side of the board is dedicated to
ground planes, while signals are placed on the solder side.
Good decoupling is important when using high resolution ADCs.
VDD should be decoupled with 10 F tantalum capacitors in
parallel with 0.1 F capacitors to GND, with the system’s analog
ground to digital ground (DGND) connection being close to
the AD7171. To achieve the best results from these decoupling
components, they should be placed as close as possible to the
device, ideally right up against the device. All logic chips should
be decoupled with 0.1 F ceramic capacitors to DGND.
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