參數(shù)資料
型號(hào)： AD7118
廠商： Analog Devices, Inc.
英文描述： ECONOLINE: REC2.2-S_DRW(Z)/H* - 2.2W DIP Package- 1kVDC Isolation- Regulated Output- 4.5-9V, 9-18V, 18-36V, 36-72V Wide Input Range 2 : 1- UL94V-0 Package Material- Continuous Short Circiut Protection- Cost Effective- 100% Burned In- Efficiency to 84%
中文描述： LOGDAC的CMOS對(duì)數(shù)D / A轉(zhuǎn)換
文件頁數(shù)： 4/6頁
文件大小： 197K
代理商： AD7118
AD7118
REV. A
–4–
CIRCUIT DE SCRIPT ION
GE NE RAL CIRCUIT INFORMAT ION
T he AD7118 consists of a 17-bit R-2R CMOS multiplying D/A
converter with extensive digital input logic. T he logic translates
the 6-bit binary input into a 17-bit word which is used to drive
the D/A converter. T able I gives the nominal output voltages
(and levels relative to 0 dB = 10 V) for all possible input codes.
T he transfer function for the circuit of Figure 1 is given by:
V
O
=
V
IN
10exp
1.5
N
20
or
V
O
V
INdB
=
1.5
N
where N is the binary input for values 0 to 57. For 60
≤
N
≤
63
the output is zero. See note 3 at bottom of T able I.
Figure 1. Typical Circuit Configuration
E QUIVALE NT CIRCUIT ANALY SIS
Figure 2 shows a simplified circuit of the D/A converter section
of the AD7118 and Figure 3 gives an approximate equivalent
circuit.
T he current source I
LEAK AGE
is composed of surface and junc-
tion leakages and as with most semiconductor devices, roughly
doubles every 10
°
C–see Figure 10. T he resistor R
O
as shown in
Figure 3 is the equivalent output resistance of the device which
varies with input code (excluding all 0’s code) from 0.8R to
2R. R is typically 12 k
. C
OUT
is the capacitance due to the
N-channel switches and varies from about 50 pF to 80 pF de-
pending upon the digital input. For further information on
CMOS multiplying D/A converters refer to “Application Guide
to CMOS Multiplying D/A Converters” which is available from
Analog Devices, Publication Number G479–15–8/78.
Figure 2. Simplified D/A Circuit of AD7118
Figure 3. Equivalent Analog Output Circuit of AD7118
Digital Input
D5
00 00 00
00 00 01
00 00 10
00 00 11
00 01 00
00 01 01
00 01 10
00 01 11
00 10 00
00 10 01
00 10 10
00 10 11
00 11 00
00 11 01
00 11 10
00 11 11
01 00 00
01 00 01
01 00 10
01 00 11
01 01 00
01 01 01
01 01 10
01 01 11
01 10 00
01 10 01
01 10 10
01 10 11
01 11 00
01 11 01
01 11 10
Attenuation
dB
0
0.0
0
1.5
0
3.0
0
4.5
0
6.0
0
7.5
0
9.0
10.5
12.0
13.5
15.0
16.5
18.0
19.5
21.0
22.5
24.0
25.5
27.0
28.5
30.0
31.5
33.0
34.5
36.0
37.5
39.0
40.5
42.0
43.5
45.0
N
0
0
0
1
0
2
0
3
0
4
0
5
0
6
0
7
0
8
0
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
2
5
26
27
28
29
30
D0
V
OUT1
10.00
8.414
7.079
5.957
5.012
4.217
3.548
2.985
2.512
2.113
1.778
1.496
1.259
1.059
0.891
0.750
0.631
0.531
0.447
0.376
0.316
0.266
0.224
0.188
0.158
0.133
0.112
0.0944
0.0794
0.0668
0.0562
N
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
Digital Input
01 11 11
10 00 00
10 00 01
10 00 10
10 00 11
10 01 00
10 01 01
10 01 10
10 01 11
10 10 00
10 10 01
10 10 10
10 10 11
10 11 00
10 11 01
10 11 10
10 11 11
11 00 00
11 00 01
11 00 10
11 00 11
11 01 00
11 01 01
11 01 10
11 01 11
11 10 00
11 10 01
11 10 10
11 10 11
11 11 X X
2
Attenuation
46.5
48.0
49.5
51.0
52.5
54.0
55.5
57.0
58.5
60.0
61.5
63.0
64.5
66.0
67.5
69.0
70.5
72.0
73.5
75.0
76.5
78.0
79.5
81.0
82.5
84.0
85.5
87.0
88.5
∞
V
OUT1
0.0473
0.0398
0.0335
0.0282
0.0237
0.0200
0.0168
0.0141
0.0119
0.0100
0.00841
0.00708
0.00596
0.00501
0.00422
0.00355
0.00299
0.00251
0.00211
0.00178
0.00150
0.00126
0.00106
0.000891
0.000750
0.000631
0.000531
0.000447
0.000376
NOT ES
1
V
= –10 V dc
2
X = 1 or 0. Output is fully muted for N
≥
60
3
Monotonic operation is not guaranteed for N = 58, 59
T able I. Ideal Attenuation vs. Input Code
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