參數(shù)資料
型號(hào)： AD7013ARS
廠商： ANALOG DEVICES INC
元件分類： 通信及網(wǎng)絡(luò)
英文描述： CMOS TIA IS-54 Baseband Receive Port
中文描述： SPECIALTY TELECOM CIRCUIT, PDSO28
封裝： SSOP-28
文件頁(yè)數(shù)： 6/20頁(yè)
文件大?。?/td> 591K
代理商： AD7013ARS
–6–
REV. A
AD7013
Limit at
T
A
= –40
°
C to +85
°
C
Parameter
Units
Description
t
1
t
2
t
3
t
4
160
65
65
20
60
2t
1
t
1
–20
t
1
–20
25
10
16t
5
25
10
0
25
25
25
ns min
ns min
ns min
ns min
ns max
ns
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns max
ns max
ns max
MCLK Cycle Time
MCLK High Time
MCLK Low Time
MCLK Rising Edge to DxCLK Rising Edge Propagation Delay
t
5
t
6
t
7
t
8
t
9
t
10
t
11
t
12
t
13
DxCLK Cycle Time
DxCLK Minimum High Time
DxCLK Minimum Low Time
DxCLK Rising Edge to FRAME IN Setup Time
DxCLK Rising Edge to FRAME IN Hold Time
FRAME IN Cycle Time
DxCLK Rising Edge to DATA IN Setup Time
DxCLK Rising Edge to DATA IN Hold Time
FRAME IN Rising Edge to FRAME OUT Rising Edge Propagation Delay
t
14
t
15
MODE1 Low to FRAME OUT 3-STATE
MODE1 High to FRAME OUT Active
NOTE
1
t
is derived from the measured time taken by the FRAME OUT pin to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then
extrapolated back to remove the effects of charging or discharging the 80 pF capacitor. This means that the time quoted in the Timing Characteristics is the
(V
AA
= +5 V
±
10%; V
DD
= +5 V
±
10%; AGND = DGND =0 V,
f
MCLK
= 6.2208 MHz; T
A
= T
MIN
to T
MAX
, unless otherwise noted)
CONTROL SERIAL INTERFACE TIMING
1
MxCLK (I)
DxCLK (O)
DATA IN (I)
NOTE: (O) INDICATES AN OUTPUT, (I) INDICATES AN INPUT, MODE1 = LOGIC HIGH
MODE1 (I)
t
14
t
15
FRAME OUT (O)
t
13
FRAME IN (I)
t
8
t
10
DATA
DB9
DB8
DB1
DB0
A3
A0
S1
S0
ADDRESS
IGNORED
t
11
t
12
t
4
t
1
t
2
t
3
t
9
t
6
t
7
3 – STATE
t
5
Figure 2. 16-Bit Serial Interface for Writing to the AD7013 Internal Registers
1.6mA
I
OL
C
L
50pF
TO OUTPUT PIN
+2.1V
I
OH
200
μ
A
Figure 1. Load Circuit for Digital Outputs
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