參數(shù)資料
型號(hào): AD7013
廠商: Analog Devices, Inc.
英文描述: CMOS TIA IS-54 Baseband Receive Port(CMOS 基帶接收口)
中文描述: 電信行業(yè)協(xié)會(huì)的CMOS的IS - 54帶接收端口(的CMOS基帶接收口)
文件頁數(shù): 2/20頁
文件大?。?/td> 599K
代理商: AD7013
Parameter
AD7013A
Units
Test Conditions/Comments
RECEIVE SECTION
ADC SPECIFICATION
Number of Input Channels
4
(IRx–IRx) and
QRx–QRx); CR12 = 0
(AUX IRx–AUX IRx) and
(AUX QRx–AUX QRx); CR12 = 1
Number of ADC Channels
Resolution
ADC Signal Range
Differential Signal Range
2
15
2.6
V
BIAS
±
0.65
Bits
Volts p-p
Volts
Measured Using an Input Sine Wave of 3 kHz
For Both Noninverting and
Inverting Analog Inputs
For Noninverting Analog Inputs;
Inverting Analog Inputs = V
BIAS
Differential
Single-Ended
Single-Ended Signal Range
V
BIAS
±
1.3
Volts
V
BIAS
0.65 to (V
AA
–0.65)
1.3 to (V
AA
–1.3)
±
7.5
Volts min/max
Volts min/max
%
Input Range Accuracy
Accuracy
Bias Offset Error
±
7.5
±
55
mV
mV
Autocalibration; V
BIAS
= min/max
User Calibration; I & Q Offset
Adjust Registers Equal to Zero
Dynamic Specifications
CMRR
–40
dB typ
Measured Using an Input Sine Wave of
3 kHz with Both Noninverting and
Inverting Inputs Tied Together
Digital Mode Filter; CR11 = 0
Analog Mode Filter; CR11 = 1
Digital Mode Filter; CR11 = 0
Dynamic Range
70
65
65
68
60
63
1.5552/1.28
97.2/80
dB typ
dB typ
dB min
dB typ
dB min
dB typ
MHz
kHz
SNR
2
Analog Mode Filter; CR11 = 1
Input Sampling Rate
Output Word Rate
MCLK = 6.2208 MHz/5.12 MHz; MCLK/4
MCLK = 6.2208 MHz/5.12 MHz;
4
×
Sampling of the Symbol Rate, MCLK/64
MCLK = 6.2208 MHz/5.12 MHz;
2
×
Sampling of the Symbol Rate, MCLK/128
48.6/40
kHz
RECEIVE DIGITAL FILTERS
Digital Mode
Root-Raised-Cosine
Settling Time
Absolute Group Delay
Frequency Response
0–7.8975 kHz
11.9 kHz
16.4025 kHz
> 30 kHz
Analog Mode
Brick Wall Filter
Settling Time
Absolute Group Delay
Frequency Response
0–8 kHz
11.4 kHz
15 kHz
>17 kHz
MCLK = 6.2208 MHz
α
= 0.35
329.2
164.6
μ
s
μ
s
±
0.05
–3.0
–19
–66
dB max
dB
dB
dB max
MCLK = 5.12 MHz
400
200
μ
s
μ
s
0 to –0.5
–3.0
–24
–68
dB max
dB
dB
dB max
TIA IS-54 RECEIVE SPECIFICATIONS
Error Vector Magnitude
3
Error Offset Magnitude
3
2
1
% rms typ
% rms typ
Measured Using a Full-Scale Input
(V
AA
= V
DD
= +5 V
±
10%; AGND = DGND = 0 V; f
MCLK
= 6.2208 MHz;
T
A
= T
MIN
to T
MAX
, unless otherwise noted)
–2–
REV.
A
AD7013–SPECIFICATIONS
1
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