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參數(shù)資料
| 型號： | AD7013 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | CMOS TIA IS-54 Baseband Receive Port(CMOS 基帶接收口) |
| 中文描述： | 電信行業(yè)協(xié)會的CMOS的IS - 54帶接收端口（的CMOS基帶接收口） |
| 文件頁數(shù)： | 15/20頁 |
| 文件大?。?/td> | 599K |
| 代理商： | AD7013 |
REV. A
AD7013
–15–
ADC Sampling Vernier
Also included in the digital filter is the means to vary the sampling
instant, as Figure 20 illustrates. The absolute group delay can be
varied from a minimum of four symbols to a maximum of four and
a half symbols allowing the user to define the sampling instant to a
resolution 1/32 of the symbol rate. The vernier can be used to
seek the optimum sampling instant for minimum Inter-Symbol-
Interference (ISI).
VERNIER = N
0
≤
N
≤
15
VERNIER = 0
L SAMPLING PERIOD = 128 x
t
1
8 x t
1
x N
VERNIER = 0
HIGH SAMPLING RATE; CR10 = 1
SAMPLING PERIOD = 64 x
t
1
8 x
t
1
x N
VERNIER = N
0
≤
N
≤
7
TIME
TIME
Figure 20. I and Q ADC Sampling Vernier for 2
×
the
Symbol Rate and 4
×
the Symbol Rate
A 4-bit vernier register is used to set the sampling instant for both
the I and Q receive ADCs. When the vernier register is pro-
grammed with zero the ADCs will have a minimum group delay of
approximately 165
μ
s. Nonzero values in the vernier register will
add additional group delay thereby moving the sampling instant for
both ADCs. After programming the sampling vernier it takes eight
symbols (
≈
330
μ
s) for the digital filter to settle. When the ADC is
operating at the high rate, vernier values from 8 to 15 yield similar
sampling instants as vernier values from 0 to 7, but delayed by an
additional 1/4 of a symbol period.
Table III. Loading Sequence for the 16-Bit Interface
DB9–DB0
A3–A0
S1, S0
Action
D9–D0
Destination Address
Ignored
Destination Reg
←
D9–D0
Table IV. Loading Sequence for the 6-Bit Interface
DB9–DB0
A3–A0
S1, S0
Action
Ignored
Ignored
Ignored
Ignored
Ignored
0011
Destination Address
Destination Address
Destination Address
Destination Address
D9, D8
D7, D6
D5, D4
D3, D2
D1, D0
D9
←
S1 and D8
←
S0
D7
←
S1 and D6
←
S0
D5
←
S1 and D4
←
S0
D3
←
S1 and D2
←
S0
D1
←
S1 and D0
←
S0
Destination Reg
←
D9–D0
Receive Section Digital Interface
The receive interface can be connected to DSP processors requiring
the use of only one serial port. The 15-bit I and Q samples are
made available as 16-bit words, where the last bit in each word is an
I/Q flag bit.
The serial data is made available on the RxDATA pin, with the I/Q
flag indicating whether the 16-bit word being clocked out is an I
sample or a Q sample. Although the I data is clocked out before
the Q data, internally both samples are processed together. The
receive interface (RxCLK, RxFRAME & RxDATA) can be 3-
Stated by setting CR18 to zero, CR18 should be set high for
normal operation.
When the receive section is put into sleep mode, by setting CR14 to
zero, the receive interface will complete the current IQ cycle before
entering into a low power sleep mode.
High Sampling Rate (CR10 =1)
The timing diagram for the receive interface is shown in Figure 3.
The output word rate per channel is equal to 97.2 kHz (MCLK/64)
which corresponds to 4 times the symbol rate.
When the receive section is brought out of sleep mode (CR14 = 1),
the receive section will initiate an offset autocalibration routine if
CR13 = 0. Once the receive offset calibration routine is complete
then RxCLK will continuously shift out I and Q data, always
beginning with I data. RxFRAME provides a framing signal that is
used to indicate the beginning of an I or Q, 16-bit data word that is
valid on the next falling edge of RxCLK. On coming out of sleep,
RxFRAME goes high one clock cycle before the beginning of I
data, and subsequently goes high in the same clock cycle as the last
bit of each 16-bit word (both I and Q). RxDATA is valid on the
falling edge of RxCLK and is clocked out MSB first, with the I/Q
flag bit indicating whether the 16-bit word is an I sample or a Q
sample.
DxCLK (O)
DATA IN (I)
A3
FRAME IN (I)
NOTE: (O) INDICATES AN OUTPUT, (I) INDICATES AN INPUT
A2
A1
A0
IGNORED
ADDRESS
DB9
DB0
DATA
S1
S0
Figure 21. 6-Bit Serial Interface for Internal AD7013 Registers
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| AD7013ARS | 制造商:AD 制造商全稱:Analog Devices 功能描述:CMOS TIA IS-54 Baseband Receive Port |
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