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參數(shù)資料
| 型號： | AD7008AP20 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 數(shù)字信號處理外設 |
| 英文描述： | M83723 14C 14#16 SKT PLUG |
| 中文描述： | 1-BIT, DSP-NUM CONTROLLED OSCILLATOR, PQCC44 |
| 封裝： | PLASTIC, LCC-44 |
| 文件頁數(shù)： | 11/16頁 |
| 文件大小： | 505K |
| 代理商： | AD7008AP20 |
AD7008
REV. B
–11–
{This section converts the twos complement au-
dio into offset binary scaled for modulating
the AD7008. If twos complement is used, the
modulation scheme will instead be double side-
band, suppressed carrier.}
r5 = 0x80000000;
r6 = r6 xor r5;
r6 = lshift r6 by -1;
r6 = r6 xor r5;
r4 = lshift r6 by -6;
{Load parallel assembly register with modula-
tion data. Q portion set to midscale, I
portion with scaled data}
r5 = 0x00000004;
dm(dds_para) = r5;
dm(dds_para) = r4;
{Transfer parallel assembly register to IQMOD
register}
r4 = 0xb0000000;
dm(dds_cont) = r4;
rti;
Many applications require precise control of the output ampli-
tude, such as in local oscillators, signal generators and modula-
tors. There are several methods to control signal amplitude.
The most direct is to program the amplitude using the IQMOD
register on the AD7008. Other methods include selecting the
load resistor value or changing the value of R
SET
. Another op-
tion is to place a voltage out DAC on the ground side of R
SET
as
in Figure 16. This allows easy control of the output amplitude
without affecting other functions of the AD7008. Any combina-
tion of these techniques may be used as long as the full-scale
voltage developed across the load does not exceed 1 volt.
cillator application is with the AD607 Monoceiver(tm). This
unique two chip combination provides a complete receiver sub-
system with digital frequency control, RSSI and demodulated
outputs for AM, FM and complex I/Q (SSB or QAM). (See
Figure 13.)
Direct Digital Modulator
In addition to the basic DDS function provided by the AD7008,
the device also offers several modulation capabilities useful in a
wide variety of application. The simplest modulation scheme is
frequency shift keying or FSK. In this application, each of the
two frequency registers is loaded with a different value, one rep-
resenting the space frequency and the other the mark frequency.
The digital data stream is fed to the FSELECT pin causing
the AD7008 to modulate the carrier frequency between the two
values.
FREQ 0
REG
FREQ 1
REG
32
32
32
MUX
32
0
1
1
0
0
F SELECT
CLOCK
PHASE
ACCUMULATOR
AD7008
Figure 14. FSK Modulator
The AD7008 has three registers that can be used for modula-
tion. Besides the example of frequency modulation shown
above, the frequency registers can be updated dynamically as
can the phase register and the IQMOD register. These can be
modulated at rates up to 16.5 MHz. The example shown below
along with code fragment shows how to implement the AD7008
in an amplitude modulation scheme. Other modulation
schemes can be implemented in a similar fashion.
SIN/COS
ROM
SIN
COS
DSP:
SCALE
ANALOG
INPUT TO
FULL
SCALE
I MOD
ADC
Q MOD
10
10
10
10
10
10
10-BIT DAC
IOUT
IOUT
10
10
0
AD7008
Figure 15. Amplitude Modulation
{__________IRQ3 Interrupt Vector__________}
{in_audio is a port used to sample the audio
signal. This signal is assumed to be twos
complement. This interrupt should be serviced
at an audio sample rate. This routine assumes
that the AD7008 has been set up with the Ampli-
tude Modulation Enabled.}
irq3_asserted:
{Get audio sample}
r6=dm(in_audio);
C1
0.1μF
6
4
5
Y7
Y6
Y5
Y4
Y3
Y2
Y1
Y0
7
9
10
11
12
13
14
15
G1
G
2A
G
2B
+5V
DMS1
DMWR
R5
390
C2
0.1μF
DMD24
DMD25
DMD26
DMD27
DMD28
DMD29
DMD30
DMD31
DMD32
DMD33
DMD34
DMD35
DMD36
DMD37
DMD38
DMD39
19
20
21
22
23
24
25
26
8
9
10
11
12
13
14
15
16
27
32
33
34
35
36
41
42
31
30
38
37
DMS3
DMD36
DMD37
DMD38
DMD39
RESET
V
CC
V
EE
7
50MHz
U2
+5V
K1115
14
OUT
V
REF
COMP
IOUT
IOUT
FSADJUST
V
AA
V
DD
V
DD
V
DD
AGND
DGND
DGND
DGND
DGND
TEST
44
7
18
29
43
40
3
17
28
39
+5V
+5V
+5V
+5V
4
5
6
+5V
+5V
R4
49.9
2
1
R3
49.9
C
B
A
DMA02
DMA01
DMA00
3
2
1
U1
74HC138
U3
AD7008
8
VOLTAGE OUT DAC,
i.e., AD7245A
0 TO +1 VOLTS
Ifs =6233 x (V
REF
–V
DAC
)
R
SET
DMDXX–DATA BITS
DMAXX–ADDRESS BITS
CS
TC0
TC1
TC2
TC3
LOAD
SCLK
SDATA
FSELECT
CLK
RESET
SLEEP
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
WR
Figure 16. External Gain Adjustment
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