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參數(shù)資料
| 型號： | AD7002AS |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 無繩電話/電話 |
| 英文描述： | LC2MOS GSM Baseband I/O Port |
| 中文描述： | TELECOM, CELLULAR, BASEBAND CIRCUIT, PQFP44 |
| 封裝： | PLASTIC, QFP-44 |
| 文件頁數(shù)： | 14/16頁 |
| 文件大?。?/td> | 455K |
| 代理商： | AD7002AS |
AD7002
–14–
REV. B
AUXILIARY DACS
Three auxiliary DACs are provided for extra control functions
such as automatic gain control, automatic frequency control or
for ramping up/down the transmit power amplifiers during the
beginning/end of a transmit burst. The three auxiliary DACs,
AUX DAC1, AUX DAC2 and AUX DAC3, have resolutions of
9-, 10- and 8-bits, respectively. In addition to the three auxiliary
DACs, the auxiliary section contains a digital output flag
(AUX FLAG) with three-state control. Communication and
sleep control of the auxiliary section is totally independent of
either the transmit or receive sections.
The AD7002 AUX DACs are voltage mode DACs, consisting
of R–2R ladder networks (Figure 20 shows AUX DAC1 archi-
tecture), constructed from highly stable thin-films resistors and
high speed single pole, double throw switches. This design
architecture leads to very low DAC current during normal
operation. However, the AUX DACs have a high output
impedance (typical 8 k
) and hence require external buffering.
The AUX DACs have an output voltage range of 0 V to V
REF
–
1 LSB. Each AUX DAC can be individually entered into low-
power sleep mode, simply by loading all ones or all zeros to that
particular AUX DAC. This does not affect the normal operation
of AUX DACs, as either of these two codes (all 0s = 0
μ
A, all
1s = 50
μ
A typical) represent the operating points for lowest
power consumption.
2R
R
2R
R
R
2R
2R
AGND
2R
DB0
DB1
DB6
DB7
DB8
2R
R
R
SHOWN FOR ALL 1s ON DAC
VREF
AUX DAC1
Figure 20. Auxiliary DAC Structure
The digital AUX FLAG output is available for any external
logic control that may be required. For instance, the AUX
FLAG could be used to control the Tx SLEEP pin, turning on
24
t
23
CLK1, CLK2 (I)
Rx SLEEP1 (I)
Rx SLEEP2 (I)
Rx CLK (O)
Rx SYNC (O)
I DATA (O)
Q DATA (O)
I MSB
I LSB
I MSB
I LSB
t
30
t
31
Q MSB
Q LSB
Q MSB
Q LSB
NOTE: (I) = DIGITAL INPUT; (O) = DIGITAL OUTPUT
t
32
t
33
t
34
t
34
t
29
t
27
t
28
t
25
t
26
Figure 19. MODE 1 RATE 0 Receive Timing
the transmit section prior to ramping up (using one of AUX
DACs) the RF amplifiers.
AUX DAC DIGITAL INTERFACE
Communication with the auxiliary section is accomplished via a
three-pin serial interface, as the timing diagram in Figure 22
illustrates. While AUX LATCH is low, data is clocked into a
16-bit shift register via the AUX DATA and AUX CLK pins.
AUX DATA is clocked on the falling edge of AUX CLK, MSB
first. The 16-bit shift register is organized as a data field (DB0–
DB9) and as a control field (DB10–DB15). The data field is
8-, 9- or 10-bits wide, depending on the AUX DAC being
loaded. The control field indicates which AUX DACs are being
loaded and also determines the state of the AUX FLAG pin.
When the shift register has been loaded, AUX LATCH is
brought high to update the selected AUX DACs and the AUX
FLAG pin. The control bits are active high, and since a control
bit has been assigned to each AUX DAC, this facilitates the
simultaneous loading of more than one AUX DAC (with the
same data). DB10, DB11 and DB12 selected AUX DAC3,
AUX DAC1 and AUX DAC2 respectively, and DBlS deter-
mines the logic state of AUX FLAG while DB14 determines
whether the three-state driver is enabled.
AUX
LATCH
AUX
CLK
AUX
DATA
16-BIT SHIFT REGISTER
AUXDAC SELECT
9-BIT AUX DAC1
10-BIT AUX DAC2
8-BIT AUX DAC3
AUX DAC1
AUX DAC2
AUX DAC3
DB0–DB9
DB13
DB15
DB14
DB12
DB11
DB10
EN
FLAG
AUX FLAG
A10-BIT
AU8-BIT
AU9-BIT
Figure 21. Auxiliary Section Serial Interface
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