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參數(shù)資料
| 型號(hào)： | AD7002AS |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 無繩電話/電話 |
| 英文描述： | LC2MOS GSM Baseband I/O Port |
| 中文描述： | TELECOM, CELLULAR, BASEBAND CIRCUIT, PQFP44 |
| 封裝： | PLASTIC, QFP-44 |
| 文件頁數(shù)： | 10/16頁 |
| 文件大小： | 455K |
| 代理商： | AD7002AS |
AD7002
–10–
REV. B
RECEIVE SECTION
The receive section consists of I and Q receive channels, each
comprised of a simple switched capacitor filter followed by a
12-bit sigma-delta ADC. The data is available on a flexible
serial interface, interfacing easily to most DSPs. The data can be
configured to be one of two formats and is also available at two
sampling rates. Onboard digital filters, which form part of the
sigma-delta ADCs, also perform critical system level filtering.
Their amplitude and phase response characteristics provide
excellent adjacent channel rejection. The receive section is also
provided with a low power sleep mode to place the receive sec-
tion on standby between receive bursts, drawing only minimal
current.
Switched Capacitor Input
The receive section analog front end is sampled at 13 MHz by a
switched capacitor filter. The filter has a zero at 6.5 MHz as
shown in Figure 11a. The receive channel also contains a digital
low-pass filter (further details are contained in the following
section) that operates at a clock frequency of 6.5 MHz. Due to
the sampling nature of the digital filter, the pass band is re-
peated about the operating clock frequency and at multiples of
the clock frequency (Figure 11b). Because the first null of the
switched capacitor filter coincides with the first image of the
digital filter, this image is attenuated by an additional 30 dBs
(Figure 11c), further simplifying the external antialiasing re-
quirements.
6.5
13
19.5
MHz
6.5
13
19.5
MHz
6.5
13
19.5
MHz
0dB
0dB
0dB
–30dB
MAX
FRONT-END
ANALOG FILTER
TRANSFER FUNCTION
DIGITAL FILTER
TRANSFER FUNCTION
SYSTEM FILTER
TRANSFER FUNCTION
a.
b.
c.
Figure 11. Switched Capacitor Input
SIGMA-DELTA ADC
The AD7002 receive channels employ a sigma-delta conversion
technique that provides a high resolution 12-bit output for both
I and Q channels, with system filtering being implemented
on-chip.
The output of the switched capacitor filter is continuously
sampled at 6.5 MHz (master clock/2) by a charge balanced
modulator, and is converted into a digital pulse train whose duty
cycle contains the digital information. Due to the high oversam-
pling rate, which spreads the quantization noise from 0 MHz to
3.25 MHz (F
S
/2), the noise energy contained in the band of
interest is reduced (Figure 12a). To reduce the quantization still
further, a high order modulator is employed to shape the noise
spectrum, so that most of the noise energy is shifted out of the
band of interest (Figure 12b).
The digital filter that follows the modulator removes the large
out-of-band quantization noise (Figure 12c), while converting
the digital pulse train into parallel 12-bit-wide binary data. The
12-bit I and Q data is made available, via a serial interface, in a
variety of formats.
FS/2
3.25 MHz
FS/2
3.25 MHz
BAND OF
INTEREST
BAND OF
INTEREST
FS/2
3.25 MHz
BAND OF
INTEREST
DIGITAL FILTER
CUTOFF FREQUENCY = 122 kHz
NOISE SHAPING
QUANTIZATION NOISE
a.
b.
c.
Figure 12. Sigma-Delta ADC
DIGITAL FILTER
The digital filters used in the AD7002 receive section carry out
two important functions. First, they remove the out-of-band
quantization noise that is shaped by the analog modulator. Sec-
ond, they are also designed to perform system level filtering,
providing excellent rejection of the neighboring channels.
Digital filtering has certain advantages over analog filtering.
First, since digital filtering occurs after the A/D conversion
process, it can remove noise injected during the conversion
process. Analog filtering cannot do this. Second, the digital filter
combines low passband ripple with a steep rolloff, while also
maintaining a linear phase response. This is very difficult to
achieve with analog filters.
Analog filtering can, however, remove noise superimposed on
the analog signal before it reaches the ADC. Digital filtering
cannot do this and noise peaks riding on signals near full scale
have the potential to saturate the analog modulator, even
though the average value of the signal is within limits. To allevi-
ate this problem, the AD7002 has overrange headroom built
into the sigma-delta modulator and digital filter which allows
overrange excursions of 100 mV.
Filter Characteristics
The digital filter is a 288-tap FIR filter, clocked at half the mas-
ter clock frequency. The frequency response is shown in Figure
14. The 3 dB point is at 122 kHz.
Due to the low pass nature of the receive filters, there is a
settling time associated with step input functions. Output data
will not be meaningful until all the digital filter taps have been
loaded with data samples taken after the step change. Hence
the AD7002 digital filters have a settling time of 44.7
μ
s
(288
3
2 t
1
).
When coming out of sleep, the digital filter taps are reset. Hence
data, initially generated by the digital filters, will not be correct.
Not until all 288 taps have been loaded with meaningful data
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