參數(shù)資料
型號(hào)： AD698SQ
廠商： ANALOG DEVICES INC
元件分類： 位置變換器
英文描述： ECONOLINE: REC2.2-S_DRW(Z)/H* - 2.2W DIP Package- 1kVDC Isolation- Regulated Output- 4.5-9V, 9-18V, 18-36V, 36-72V Wide Input Range 2 : 1- UL94V-0 Package Material- Continuous Short Circiut Protection- Cost Effective- 100% Burned In- Efficiency to 84%
中文描述： SIGNAL CONDITIONER, CDIP24
封裝： DOUBLE WIDTH, CERAMIC, DIP-24
文件頁(yè)數(shù)： 8/12頁(yè)
文件大?。?/td> 228K
代理商： AD698SQ
REV. B
–8–
AD698
Note that V
OS
should
be chosen so that R3 cannot have negative
value .
Figure 12 shows the desired response.
V
OUT
(VOLTS)
+5
+0.1d (INCHES)
–0.1
+10
Figure 12. V
OUT
(0 V–10 V Full Scale) vs. Displacement
(
±
0.1 Inch)
DE SIGN PROCE DURE
SINGLE SUPPLY OPE RAT ION
Figure 13 shows the single supply connection method.
R1
C1
C2
C3
R4
R3
13
16
15
14
24
23
22
21
20
19
18
17
12
11
10
9
8
1
2
3
4
7
6
5
AD698
–V
S
EXC1
EXC2
LEV1
LEV2
FREQ1
BFILT1
BFILT2
–BIN
+BIN
–AIN
FREQ2
SIG REF
OFFSET2
OFFSET1
+V
S
OUT FILT
FEEDBACK
SIG OUT
–ACOMP
AFILT2
AFILT1
+ACOMP
+AIN
C4
R2
1000pF
SIGNAL
REFERENCE
R
L
V
OUT
0.1μF
V
ps
+30V
6.8μF
1M
R6
R5
C5
A
B
C
D
PHASE
LAG/LEAD
NETWORK
R
T
A
B
C
D
PHASE LEAD
R
S
C
C
R
S
R
S
R
T
A
B
C
D
PHASE LAG
C
PHASE LAG = Arc Tan (Hz RC);
PHASE LEAD = Arc Tan 1/(Hz RC)
WHERE R = R
S
// (R
S
+ R
T
)
Figure 13. Interconnection Diagram for Single Supply
Operation
For single supply operation, repeat Steps 1 through 10 of the
design procedure for dual supply operation. R5, R6 and C5 are
additional component values to be determined. V
OUT
is mea-
sured with respect to SIGNAL REFERENCE.
10. Compute a maximum value of R5 and R6 based upon the
relationship
R
5 +
R
6
≤
V
PS
/100
μ
A
11. T he voltage drop across R5 must be greater than
2
+
10
k
1.2
V
R
4
+
2
k
+
250
μ
A
+
V
OUT
4
×
R
2
Volts
T herefore
R
5
≥
2
+
10
k
1.2
V
R
4
+
2
k
+
250
μ
A
+
100
μ
A
V
OUT
4
×
R
2
Ohms
Based upon the constraints of R5 + R6 (Step 10) and R5 (Step
11), select an interim value of R6.
12. Load current through R
L
returns to the junction of R5 and
R6, and flows back to V
PS
. Under maximum load condi-
tions, make sure the voltage drop across R5 is met as de-
fined in Step 11.
As a final check on the power supply voltages, verify that
the peak values of V
A
and V
B
are at least 2.5 volts less than
the voltage between +V
S
and –V
S
.
13. C5 is a bypass capacitor in the range of 0.1
μ
F to 1
μ
F.
Gain Phase Characteristics
T o use an LVDT in a closed-loop mechanical servo application,
it is necessary to know the dynamic characteristics of the trans-
ducer and interface elements. T he transducer itself is very quick
to respond once the core is moved. T he dynamics arise prima-
rily from the interface electronics. Figures 14, 15 and 16 show
the frequency response of the AD698 LVDT Signal Conditioner.
Note that Figures 15 and 16 are basically the same; the differ-
ence is frequency range covered. Figure 15 shows a wider range
of mechanical input frequencies at the expense of accuracy.
FREQUENCY – Hz
0
10k
100
1k
10
0
–30
–60
–70
0
–10
–20
–50
–40
G
–360
–60
–240
–300
–420
–180
–120
P
0.1μF
0.33μF
2.0μF
R2 = 81k
f
EXC
= 2.5kHz
0.1μF
0.33μF
2.0μF
R2 = 81k
f
EXC
= 2.5kHz
Figure 14. Gain and Phase Characteristics vs. Frequency
(0 kHz–10 kHz)
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