參數(shù)資料
型號： AD6653BCPZ-150
廠商： ANALOG DEVICES INC
元件分類： 無繩電話/電話
英文描述： IF Diversity Receiver
中文描述： TELECOM, CELLULAR, BASEBAND CIRCUIT, QCC64
封裝： 9 X 9 MM, ROHS COMPLIANT, MO-220VMMD-4, LFCSP-64
文件頁數(shù)： 9/80頁
文件大?。?/td> 1998K
代理商： AD6653BCPZ-150
AD6653
SWITCHING SPECIFICATIONS
Table 4.
Rev. 0 | Page 9 of 80
AD6653BCPZ-125
Min
Typ
20
10
8
2.4
4
3.6
4
1.6
0.8
AD6653BCPZ-150
Min
Typ
20
10
6.66
2.0
3.33
3.0
3.33
1.6
0.8
Parameter
CLOCK INPUT PARAMETERS
Input Clock Rate
Conversion Rate
1
DCS Enabled
DCS Disabled
CLK Period—Divide-by-1 Mode (t
CLK
)
CLK Pulse Width High (t
CLKH
)
Divide-by-1 Mode, DCS Enabled
Divide-by-1 Mode, DCS Disabled
Divide-by-2 Mode, DCS Enabled
Divide-by-3 Through Divide-by-8 Modes,
DCS Enabled
DATA OUTPUT PARAMETERS (DATA, FD)
CMOS Noninterleaved Mode—DRVDD = 1.8 V
Data Propagation Delay (t
PD
)
2
DCO Propagation Delay (t
DCO
)
Setup Time (t
S
)
Hold Time (t
H
)
CMOS Noninterleaved Mode—DRVDD = 3.3 V
Data Propagation Delay (t
PD
)
2
DCO Propagation Delay (t
DCO
)
Setup Time (t
S
)
Hold Time (t
H
)
CMOS Interleaved and IQ Mode—DRVDD = 1.8 V
Data Propagation Delay (t
PD
)
2
DCO Propagation Delay (t
DCO
)
Setup Time (t
S
)
Hold Time (t
H
)
CMOS Interleaved and IQ Mode—DRVDD = 3.3 V
Data Propagation Delay (t
PD
)
2
DCO Propagation Delay (t
DCO
)
Setup Time (t
S
)
Hold Time (t
H
)
LVDS Mode—DRVDD = 1.8 V
Data Propagation Delay (t
PD
)
2
DCO Propagation Delay (t
DCO
)
Pipeline Delay (Latency) NCO, FIR, f
S
/8 Mix Disabled
Pipeline Delay (Latency) NCO Enabled; FIR and f
S
/8
Mix Disabled (Complex Output Mode)
Pipeline Delay (Latency) NCO, FIR Filter, and f
S
/8 Mix
Enabled
Aperture Delay (t
A
)
Aperture Uncertainty (Jitter, t
J
)
Wake-Up Time
3
OUT-OF-RANGE RECOVERY TIME
1
Conversion rate is the clock rate after the divider.
2
Output propagation delay is measured from CLK 50% transition to DATA 50% transition, with a 5 pF load.
3
Wake-up time is dependent on the value of the decoupling capacitors.
Temperature
Full
Full
Full
Full
Full
Full
Full
Full
Max
625
125
125
5.6
4.4
Max
625
150
150
4.66
3.66
Unit
MHz
MSPS
MSPS
ns
ns
ns
ns
ns
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
1.6
4.0
1.9
4.4
1.6
3.4
1.9
3.8
2.5
3.7
3.9
5.4
9.5
6.5
4.1
5.8
9.7
6.3
3.9
4.8
4.9
3.1
4.1
5.2
5.1
2.9
4.8
5.3
38
38
6.2
7.3
6.4
7.7
6.2
6.7
6.4
7.1
7.0
7.3
1.6
4.0
1.9
4.4
1.6
3.4
1.9
3.8
2.5
3.7
3.9
5.4
8.16
5.16
4.1
5.8
8.36
4.96
3.9
4.8
4.23
2.43
4.1
5.2
4.43
2.23
4.8
5.3
38
38
6.2
7.3
6.4
7.7
6.2
6.7
6.4
7.1
7.0
7.3
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Cycles
Cycles
Full
109
109
Cycles
Full
Full
Full
Full
1.0
0.1
350
44
1.0
0.1
350
44
ns
ps rms
μs
Cycles
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