參數(shù)資料
型號(hào)： AD6655-125EBZ1
廠商： Analog Devices, Inc.
英文描述： IF Diversity Receiver
中文描述： IF分集接收機(jī)
文件頁(yè)數(shù)： 1/84頁(yè)
文件大?。?/td> 2012K
代理商： AD6655-125EBZ1
IF Diversity Receiver
AD6655
FEATURES
SNR = 74.5 dBc (75.5 dBFS) in a 32.7 MHz BW at
70 MHz @ 150 MSPS
SFDR = 80 dBc to 70 MHz @ 150 MSPS
1.8 V analog supply operation
1.8 V to 3.3 V CMOS output supply or 1.8 V LVDS
output supply
Integer 1-to-8 input clock divider
Integrated dual-channel ADC
Sample rates up to 150 MSPS
IF sampling frequencies to 450 MHz
Internal ADC voltage reference
Integrated ADC sample-and-hold inputs
Flexible analog input range: 1 V p-p to 2 V p-p
ADC clock duty cycle stabilizer
95 dB channel isolation/crosstalk
Integrated wideband digital downconverter (DDC)
32-bit complex, numerically controlled oscillator (NCO)
Decimating half-band filter and FIR filter
Supports real and complex output modes
Fast attack/threshold detect bits
Composite signal monitor
Energy-saving power-down modes
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
2007 Analog Devices, Inc. All rights reserved.
www.analog.com
APPLICATIONS
Communications
Diversity radio systems
Multimode digital receivers (3G)
TD-SCDMA, WiMax, WCDMA,
CDMA2000, GSM, EDGE, LTE
I/Q demodulation systems
Smart antenna systems
General-purpose software radios
Broadband data applications
PRODUCT HIGHLIGHTS
1.
Integrated dual, 14-bit, 150 MSPS ADC.
2.
Integrated wideband decimation filter and 32-bit
complex NCO.
3.
Fast overrange detect and signal monitor with serial output.
4.
Proprietary differential input maintains excellent SNR
performance for input frequencies up to 450 MHz.
5.
Flexible output modes, including independent CMOS,
interleaved CMOS, IQ mode CMOS, and interleaved LVDS.
6.
SYNC input allows synchronization of multiple devices.
7.
3-bit SPI port for register programming and register readback.
FUNCTIONAL BLOCK DIAGRAM
0
AVDD
FD[0:3]A
DVDD
DRVDD
AD6655
VIN+A
VIN–A
VREF
SENSE
CML
RBIAS
SHA
SYNC
FD[0:3]B
SMI
SDFS
SMI
SCLK/
PDWN
SMI
SDO/
OEB
REF
SELECT
ADC
I
Q
Q
I
VIN–B
VIN+B
D13A
D0A
CLK+
CLK–
DCOA
DCOB
D13B
D0B
SHA
ADC
MULTI-CHIP
SYNC
SIGNAL
MONITOR
DIVIDE 1
TO 8
DUTY
CYCLE
STABILIZER
AGND
SIGNAL MONITOR
INTERFACE
C
O
SIGNAL MONITOR
DATA
SDIO/
DCS
SCLK/
DFS
CSB
DRGND
SPI
PROGRAMMING DATA
FD BITS/THRESHOLD
DETECT
FD BITS/THRESHOLD
DETECT
32-BIT
TUNING
NCO
f
/8
NCO
LP/HP
DECIMATING
HB FILTER +
FIR
LP/HP
DECIMATING
HB FILTER +
FIR
C
O
DCO
GENERATION
NOTES
1.PIN NAMES ARE FOR THE CMOS PIN CONFIGURATION ONLY; SEE FIGURE 10 FOR LVDS PIN NAMES.
Figure 1.
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