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參數(shù)資料
| 型號： | AD6653-125EBZ |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | IF Diversity Receiver |
| 中文描述： | IF分集接收機 |
| 文件頁數(shù)： | 10/80頁 |
| 文件大?。?/td> | 1998K |
| 代理商： | AD6653-125EBZ |
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AD6653
TIMING SPECIFICATIONS
Rev. 0 | Page 10 of 80
Table 5.
Parameter
SYNC TIMING REQUIREMENTS
t
SSYNC
t
HSYNC
SPI TIMING REQUIREMENTS
t
DS
t
DH
t
CLK
t
S
t
H
t
HIGH
t
LOW
t
EN_SDIO
Conditions
SYNC to the rising edge of CLK setup time
SYNC to the rising edge of CLK hold time
Setup time between the data and the rising edge of SCLK
Hold time between the data and the rising edge of SCLK
Period of the SCLK
Setup time between CSB and SCLK
Hold time between CSB and SCLK
Minimum period that SCLK should be in a logic high state
Minimum period that SCLK should be in a logic low state
Time required for the SDIO pin to switch from an input to an output
relative to the SCLK falling edge
Time required for the SDIO pin to switch from an output to an input
relative to the SCLK rising edge
Delay from rising edge of CLK+ to rising edge of SMI SCLK
Delay from rising edge of SMI SCLK to SMI SDO
Delay from rising edge of SMI SCLK to SMI SDFS
Min
2
2
40
2
2
10
10
10
Typ
0.24
0.4
Max
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
DIS_SDIO
10
ns
SPORT TIMING REQUIREMENTS
t
CSSCLK
t
SSLKSDO
t
SSCLKSDFS
Timing Diagrams
3.2
0.4
0.4
4.5
0
0
6.2
+0.4
+0.4
ns
ns
ns
0
t
H
t
S
CLK+
DECIMATED
CMOS DATA
DECIMATED
FD DATA
CHANNEL A/B
FD BITS
CHANNEL A/B
FD BITS
CHANNEL A/B
FD BITS
CHANNEL A/B
DATA BITS
CHANNEL A/B
DATA BITS
CHANNEL A/B
DATA BITS
CHANNEL A/B
FD BITS
CHANNEL A/B
FD BITS
CHANNEL A/B
FD BITS
DECIMATED
DCOA/DCOB
t
PD
t
DCO
Figure 2. Decimated Noninterleaved CMOS Mode Data and Fast Detect Output Timing (Fast Detect Mode Select Bits = 000)
t
S
t
PD
t
DCO
t
H
CLK+
DECIMATED
CMOS DATA
CHANNEL A/B
DATA BITS
CHANNEL A/B
DATA BITS
DECIMATED
FD DATA
CHANNEL A/B
FD BITS
CHANNEL A/B
FD BITS
DECIMATED
DCOA/DCOB
CHANNEL A/B
DATA BITS
CHANNEL A/B
FD BITS
0
Figure 3. Decimated Noninterleaved CMOS Mode Data and Fast Detect Output Timing (Fast Detect Mode Select Bits = 001 Through Fast Detect Mode Select Bits = 100)
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| AD6653BCPZ-125 | IF Diversity Receiver |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD6653-150EBZ | 制造商:Analog Devices 功能描述:EVAL BD FOR AD6653 - Bulk |
| AD6653BCPZ-125 | 制造商:Analog Devices 功能描述:IF DIVERSITY RCVR 64LFCSP EP - Trays 制造商:Rochester Electronics LLC 功能描述: 制造商:Analog Devices 功能描述:IC RECEIVER IF DIVERSITY LFCSP64 |
| AD6653BCPZ-150 | 制造商:Analog Devices 功能描述:IF DIVERSITY RCVR 64LFCSP EP - Trays 制造商:Analog Devices 功能描述:IC RECEIVER IF DIVERSITY LFCSP64 制造商:Analog Devices 功能描述:IC, RECEIVER, IF DIVERSITY, LFCSP64 |
| AD6654 | 制造商:Analog Devices 功能描述:- Bulk |
| AD6654/PCB | 制造商:AD 制造商全稱:Analog Devices 功能描述:14-Bit, 92.16 MSPS, 4-/6-Channel Wideband IF to Baseband Receiver |
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