參數(shù)資料
型號： AD6650PCB
廠商： Analog Devices, Inc.
英文描述： Diversity IF to Baseband GSM/EDGE Narrowband Receiver
中文描述： 多樣性IF到基帶的GSM / EDGE窄帶接收器
文件頁數(shù)： 21/28頁
文件大?。?/td> 594K
代理商： AD6650PCB
Preliminary Technical Data
SDFS Modes
As mentioned in the section above, Serial Data Frame Sync,
there are either 3 or 4 modes of operation depending on how the
output of the AD6650 is configured.
Setting Bit 7 of register 0x22 high indicates that input channel A
data is output on SDO0 and input channel B is output on SDO1.
In this condition there are 3 modes of operation (There are
technically 4 modes, but mode 0 and 1 are the same):
Mode 0 and 1 (0x22 Bits 6–5:00; Bit 7:1): The SDFS is valid for
one complete clock cycle prior to the data shift. This single pulse
is valid for output channel SDO0 and SDO1. On the next clock
cycle, the AD6650 begins shifting out the digitally processed
data stream. Depending on the bit precision of the serial
configuration, either 16, or 24 bits of I data are shifted out,
followed by 16 or 24 bits of Q data.
Mode 2 (0x22 Bits 6–5:10; Bit 7:1): Since both SDO0 and
SDO1 are used, SDFS pulses high one clock cycle prior to I data
and also pulses high one clock cycle prior to Q data for each
corresponding input channel. In this mode, there will be 2 SFDS
pulses per each output channel.
Mode 3 (0x22 Bits 6–5:11; Bit 7:1): The SDFS is high for the
entire time that valid bits are being shifted. On SDO0 this will be
either 16 or 24 bits of I data, followed by 16 or 24 bits of Q data
corresponding to input channel A and for SDO1, SDFS remains
high for 16 or 24 bits of I data, followed by 16 or 24 bits of Q
data corresponding to input channel B. The SDFS bit goes high
one complete clock cycle before the first bit shifted out of the
AD6650.
Setting Bit 7 of register 0x22 low indicates that input channel A
and B data will be output to SDO0 only. In this condition there
are 4 modes of operation:
Mode 0 (0x22 Bits 6–5:00; Bit 7:0): The SDFS is valid for one
complete clock cycle prior to the data shift. There is only a
single pulse for both A and B input channels. On the next clock
cycle, the AD6650 begins shifting out the digitally processed
data stream onto SDO0. Depending on the bit precision of the
serial configuration, either 16, or 24 bits of I data, followed by
16 or 24 bits of Q data are shifted out corresponding to input
channel A and then either 16, or 24 bits of I data, followed by 16
or 24 bits of Q data corresponding to input channel B are shifted
out.
Mode 1 (0x22 Bits 6–5:01; Bit 7:0): The SDFS bit goes high one
clock cycle prior to the actual data associated with analog input
channel A. When the I and Q data stream is complete, a second
SDFS is inserted one clock cycle prior to the shift of the data
associated with analog input channel B.
Mode 2 (0x22 Bits 6–5:10; Bit 7:0): SFDS will go high for one
complete clock cycle prior to I data and a second SDFS is
inserted one clock cycle prior to the shift of the first Q bit, both
corresponding to channel A input data. A third and fourth
SDFS are inserted a clock cycle prior to the shift of I and Q data
AD6650
REV. PrJ 02/27/2003
21
respectively, which corresponds to input channel B data. In this
mode there will be a total of 4 SFDS pulses.
Mode 3 (0x22 Bits 6–5:11; Bit 7:0): The SDFS is high for the
entire time that valid bits are being shifted, and goes high one
complete clock cycle before the first bit is shifted out of the
AD6650. On SDO0 there will either 16 or 24 bits of I data,
followed by 16 or 24 bits of Q data, then 16 or 24 bits of I data,
followed by 16 or 24 bits of Q data corresponding to input
channel A and B respectively.
MICROPORT CONTROL
The AD6650 has an 8-bit microprocessor port and 4 serial
input ports. The use of each of these ports is described
separately below. The interaction of the ports is then
described. The Microport interface is a multi-mode interface
that is designed to give flexibility when dealing with the host
processor. There are two modes of bus operation: Intel non-
multiplexed mode (INM), and Motorola non-multiplexed
mode (MNM). The mode is selected based on host
processor and which mode is best suited to that processor.
The micro-port has an 8-bit data bus (D[7:0]), 3-bit address
bus(A[2:0]), 3 control pins lines (/CS, /DS or /RD, RW or
/WR), and one status pin (DTACK or RDY). The
functionality of the control signals and status line changes
slightly depending upon the mode that is chosen. Refer to
the timing diagrams and the following descriptions for
details on the operation of both modes.
External Memory Map
The External Memory Map is used to gain access to the
Channel Address Space. The 8-bit data and address buses
are used to set the 8 registers that can be seen in the
following table. These registers are collectively referred to
as the External Interface Registers since they control all
accesses to the Channel Address space as well as global chip
functions. The use of each of these individual registers is
described below in detail.
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