參數(shù)資料
型號(hào)： AD6650
廠商： Analog Devices, Inc.
英文描述： Diversity IF to Baseband GSM/EDGE Narrowband Receiver
中文描述： 多樣性IF到基帶的GSM / EDGE窄帶接收器
文件頁(yè)數(shù)： 20/28頁(yè)
文件大小： 594K
代理商： AD6650
Preliminary Technical Data
Serial Port Timing Specifications
Whether the AD6650 serial channel is operated as a Serial Bus
Master or as a Serial Slave, the serial port timing is identical.
Figures xx to xx indicate the required timing for each of the
specification.
AD6650
REV. PrJ 02/27/2003
20
t
SCLK
t
SCLKL
t
SCLKH
SCLK
Figure xx. SCLK Timing Requirements
SCLK
CLK
t
DSCLKH
t
SCLKL
t
SCLKH
Figure xx. SCLK Switching Characteristics (Divide by 1)
t
DSDO
SCLK
SDO
I
15
I
14
I
13
.....
Figure xx. Serial Output Data Switching Characteristics
t
SSF
t
HSF
SCLK
SDFS
Figure xx. SDFS Timing Requirements (SBM=0)
SCLK
SDFS
SDO
SDFS minimum
is one width
I
MS
B
I
MSB -
1
First data is available the first
SCLK arising
t
DSO
Figure xx. Timing for Serial Output Port (SBM=1)
SCLK
SCLK is an output when SBM is high; SCLK is an input when
SBM is low in serial slave mode. All outputs are switched on
the rising edge of SCLK. The SDFS pin is sampled on the
falling edge of SCLK. This allows the AD6650 to recognize the
SDFS in time to initiate a frame on the very next SCLK rising
edge. The maximum speed of this port is 52 MHz.
SDO
SDO is the Serial Data Output. Serial output data is shifted on
the rising edge of SCLK. On the very next SCLK rising edge
after an SDFS, the MSB of the I data from the channel is shifted.
On every subsequent SCLK edge a new piece of data is shifted
out on the SDO pin until the last bit of data is shifted out. The
last bit of data shifted is the LSB of the Channels Q data. SDO is
three-stated when the serial port is outside its time-slot. This
allows the AD6650 to share the SDIN of a DSP with other
AD6650s or other devices.
SDFS
SDFS is the Serial Data Frame Sync signal. SDFS is an output
when is high in the master mode. SDFS is an input when SBM is
low in the slave mode. SDFS is sampled on the falling edge of
SCLK. When SBM is sampled low, the AD6650 serial port will
function as a serial slave. In this mode, the port is silent until the
DSP issues a frame sync. When the AD6650 detects an SDFS
on the falling edge of a DSP-generated serial clock, on the next
rising edge of the serial clock, the AD6650 enables the output
driver and shifts the MSB of the I word. Data is shifted until the
LSB of the Q word has been sent.
When SBM is sampled high, the chip functions as a serial bus
master. In this mode, the AD6650 is responsible for generating
serial control data. Four modes of that operation are set via
channel address 0x22 Bits 6–5.
Serial Word Length
Bit 4 of register 0x22 determine the length of the serial word (I
or Q). If this bit is set to ‘0,’ each word is 16 bits (16 bits for I
and 16 bits for Q). If this bit is set to ‘1,’ the serial words are 24
bits wide.
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