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參數資料
| 型號： | AD6650 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Diversity IF to Baseband GSM/EDGE Narrowband Receiver |
| 中文描述： | 多樣性IF到基帶的GSM / EDGE窄帶接收器 |
| 文件頁數： | 13/28頁 |
| 文件大小： | 594K |
| 代理商： | AD6650 |
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Preliminary Technical Data
Pin Configuration
1
2
3
A
DGND
TDI
TMS
/TRST /RESET DNC AVDD
B
SDFS SCLK
TDO
TCLK
C
SD1
SD0
DVDD
DVDD
D
D7
DR
DVDD
DGND
E
D5
D6
DVDD
DGND
F
D3
D4
DVDD
DGND
G
D1
D2
DVDD
DGND
H
/DS
D0
DVDD
DGND
J
RW /DTACK DVDD
DVDD
K
A2
A1
/CS
MODE1 CHIP_ID1 DNC AVDD REFGND REFT AGND
L
DGND
A0
MODE2 MODE0 CHIP_ID0 DNC AVDD
1
2
3
4
5
AD6650
REV. PrJ 02/27/2003
13
4
5
6
7
8
9
10
AGND AGND
A
11
CLK
/CLK
SYNC
DNC AVDD
AVDD AGND AGND
/BIN
B
BIN
C
DVDD DVDD AVDD
AVDD AGND AGND
AVDD AGND AGND AGND
D
AVDD AGND AGND
AVDD AGND XVCOB XVCO
F
AVDD AGND AGND
AVDD AGND AGND AGND
H
AVDD AGND AGND
DGND DGND
AVDD
DGND DGND
AVDD
LF
E
DGND DGND
AVDD
DGND DGND
AVDD
CP
G
DGND DGND
AVDD
DVDD DVDD AVDD
AIN
J
/AIN
K
VREF
8
REFB AGND AGND
L
9
10
6
7
11
Pin Function Descriptions
Name
POWER SUPPLY
DVDD
AVDD
DGND
AGND
INPUTS
/RESET
SYNC
Type
Function
# of Pins
P
P
G
G
3.3V Digital Core/IO Supply
3.3V Analog Supply
Digital Ground
Analog Ground
13
9
17
22
I
I
Active Low Reset Pin
Synchronizes Digital Filters and AGC loop
Chip ID
1
1
CHIP_ID[1:0]
I
2
SERIAL DATA PORT
SCLK
SDFS
SD0
SD1
DR
1
MICROPORT/SERIAL CONTROL
I/O
I/O
O/T
O/T
O
Bi-directional Serial Clock
Bi-directional Serial Data Frame Sync
Serial Data Output
Serial Data Output
Output Data Ready Indicator
1
1
1
1
1
2
D[7:0]
I/O/T
Bi-directional Microport Data
8
2
1
1
1
1
1
3
A[2:1]
A0
/CS
/DS(/RD)
/DTACK(RDY)
RW(/WR)
MODE[2:0]
JTAG
I
I/O/T
I
I/O/T
I/O/T
I/O/T
I
I
Microport Address Bits 2 and 1
Microport Adress bit 0
Chip Select
Active Low Data Strobe (Active Low Read)
Active Low Data Acknowledge (Microport Status Bit)
Read Write (Active Low Write)
Selects Control Port Mode
Test Reset Pin
/TRST
1
TCLK
I
Test Clock Input
1
1
TMS
I
Test Mode Select Input
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