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參數(shù)資料
| 型號： | AD664KPZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 22/23頁 |
| 文件大小： | 0K |
| 描述： | IC DAC 12BIT QUAD MONO 44-PLCC |
| 產(chǎn)品培訓(xùn)模塊： | Data Converter Fundamentals DAC Architectures |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 設(shè)置時(shí)間： | 8µs |
| 位數(shù)： | 12 |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 4 |
| 電壓電源： | 雙 ± |
| 功率耗散（最大）： | 525mW |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 44-LCC（J 形引線） |
| 供應(yīng)商設(shè)備封裝： | 44-PLCC（16.59x16.59） |
| 包裝： | 管件 |
| 輸出數(shù)目和類型： | 4 電壓，單極；4 電壓，雙極 |
| 采樣率（每秒）： | 125k |
AD664
REV.
–8–
Table II. AD664 Digital Truth Table
Function
DS1, DS0
LS
MS
TR
QS0
, 1, 21
RD
CS
RST
Load 1st Rank (data)
DACA
00
0
1
Select Quad
1
→01
DACB
01
0
1
Select Quad
1
→01
DACC
10
0
1
Select Quad
1
→01
DACD
11
0
1
Select Quad
1
→01
Load 2nd Rank (data)
XX
1
XXX
1
→01
Readback 2nd Rank (data)
Select D/A
X
1
Select Quad
0
1
→01
Reset
XX
X
XXX
X
0
Transparent
1
All DACs
XX
1
0
000
1
→01
DACA
00
0
1
0
000
1
→01
DACB
01
0
1
0
000
1
→01
DACC
10
0
1
0
000
1
→01
DACD
11
0
1
0
000
1
→01
Mode Select
1, 2
1st Rank
XX
0
1
00X
1
→01
2nd Rank
XX
1
0
1
XXX
1
→01
Readback Mode1
XX
X
0100X
01
→01
Update 2nd Rank
and Mode
XX
1
0
XXX
1
→01
NOTES
X = Don’t Care.
1For 44-pin versions only. Allow the AD664 to be addressed in 4-bit nibble, 8-bit byte or 12-bit parallel words.
2For MS, TR, LS = 0, a MS 1st write occurs.
Figure 9a. Update Output of a Single DAC
25 CTMIN to TMAX
SYMBOL
MIN (ns)
tLS*0
0
tDS
00
tDH
00
tLW
60
80
tCH
30
50
tAS
00
tAH
00
*FOR tLS > 0, THE WIDTH OF LS MUST BE
INCREASED BY THE SAME AMOUNT THAT
tLS IS GREATER THAN 0 ns.
Figure 9b. Update Output of a Single DAC Timing
The following sections detail the timing requirements for
various data loading schemes. All of the timing specifica-
tions shown assume VIH = 2.4 V, VIL = 0.4 V, VCC = +15 V,
VEE = –15 V and VLL = +5 V.
Load and Update One DAC Output
In this first example, the object is simply to change the output of
one of the four DACs on the AD664 chip. The procedure is to
select the address bits that indicate the DAC to be programmed,
pull LATCH SELECT (LS) low, pull CHIP SELECT (CS)
low, release LS and then release CS. When CS goes low, data
enters the first rank of the input latch. As soon as LS goes high,
the data is transferred into the second rank and produces the
new output voltage. During this transfer, MS, TR, RD and RST
should be held high.
Preloading the First Rank of One DAC
In this case, the object is to load new data into the first rank of
one of the DACs but not the output. As in the previous case, the
address and data inputs are placed on the appropriate pins. LS
is then brought to “0” and then CS is asserted. Note that in this
situation, however, CS goes high before LS goes high. The in-
put data is prevented from getting to the second rank and affect-
ing the output voltage.
D
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