14-Bit, 40 MSPS/65 MSPS
Analog-to-Digital Converter
AD6644
Rev. D
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityis assumedbyAnalogDevicesforitsuse,norforanyinfringements of patents or other
rightsofthirdpartiesthatmayresultfromitsuse.Specificationssubjecttochangewithoutnotice.No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
2007 Analog Devices, Inc. All rights reserved.
FEATURES
65 MSPS guaranteed sample rate
40 MSPS version available
Sampling jitter < 300 fs
100 dB multitone SFDR
1.3 W power dissipation
Differential analog inputs
Pin compatible to AD6645
Twos complement digital output format
3.3 V CMOS compatible
Data-ready for output latching
APPLICATIONS
Multichannel, multimode receivers
AMPS, IS-136, CDMA, GSM, WCDMA
Single channel digital receivers
Antenna array processing
Communications instrumentation
Radar, infrared imaging
Instrumentation
GENERAL DESCRIPTION
The AD6644 is a high speed, high performance, monolithic 14-bit
analog-to-digital converter (ADC). All necessary functions,
including track-and-hold (TH) and reference, are included on-
chip to provide a complete conversion solution. The AD6644
provides CMOS-compatible digital outputs. It is the third
generation in a wideband ADC family, preceded by the AD9042
(12-bit 41 MSPS) and the AD6640 (12-bit 65 MSPS, IF
sampling).
Designed for multichannel, multimode receivers, the AD6644
is part of the Analog Devices, Inc. new SoftCell transceiver
chipset. The AD6644 achieves 100 dB multitone, spurious-free
dynamic range (SFDR) through the Nyquist band. This break-
through performance eases the burden placed on multimode
digital receivers (software radios) which are typically limited by
the ADC. Noise performance is exceptional; typical signal-to-
noise ratio is 74 dB.
The AD6644 is also useful in single channel digital receivers
designed for use in wide-channel bandwidth systems (CDMA,
WCDMA). With oversampling, harmonics can be placed
outside the analysis bandwidth. Oversampling also facilitates
the use of decimation receivers (such as the AD6620), allowing
the noise floor in the analysis bandwidth to be reduced. By
replacing traditional analog filters with predictable digital
components, modern receivers can be built using fewer RF
components, resulting in decreased manufacturing costs, higher
manufacturing yields, and improved reliability.
The AD6644 is built on the Analog Devices high speed
complementary bipolar process (XFCB) and uses an innovative,
multipass circuit architecture. Units are packaged in a 52-lead
plastic low profile quad flat package (LQFP) specified from –
25°C to +85°C.
PRODUCT HIGHLIGHTS
1. Guaranteed sample rate is 65 MSPS.
2. Fully differential analog input stage.
3. Digital outputs can be run on 3.3 V supply for easy interface
to digital ASICs.
4. Complete solution: reference and track-and-hold.
5. Packaged in small, surface-mount, plastic, 52-lead LQFP.
FUNCTIONAL BLOCK DIAGRAM
5
6
5
AD6644
AIN
VREF
ENCODE
GND
DMID OVR DRY D13
(MSB)
D12 D11 D10 D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
(LSB)
ADC3
TH5
TH4
DAC2
ADC2
TH3
A2
DAC1
DIGITAL ERROR CORRECTION LOGIC
TH2
ADC1
TH1
A1
2.4V
INTERNAL
TIMING
DVCC
AVCC
0
09
71
-00
1
Figure 1.