- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄373890 > AD6623AS (ANALOG DEVICES INC) 4-Channel, 104 MSPS Digital Transmit Signal Processor TSP PDF資料下載
參數(shù)資料
| 型號： | AD6623AS |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 通信及網(wǎng)絡 |
| 英文描述： | 4-Channel, 104 MSPS Digital Transmit Signal Processor TSP |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, PQFP128 |
| 封裝： | PLASTIC, MQFP-128 |
| 文件頁數(shù)： | 37/40頁 |
| 文件大小： | 381K |
| 代理商： | AD6623AS |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁當前第37頁第38頁第39頁第40頁
REV. 0
AD6623
–37–
Time Restriction CMEM Restriction
N
L
RCF
RCF
≤
×
min
1
2
,16
256
(31)
DMEM Restriction
where:
L
L
L
L
M
N
f
f
RCF
CIC
CIC
CIC
TSP
CLK
IN
=
×
×
=
×
5
2
2
(32)
De-interleaving the input data into multiple TSPs extends the
time restriction and may possibly extend the DMEM restriction,
but will not extend the CMEM restriction. Deinterleaving the
input stream to multiple TSPs divides the input sample rate to
each TSP by the number of TSPs used (N
TSP
). To keep the output
rate fixed, L must be increased by a factor of N
CH
, which extends
the time restriction. This increase in L may be achieved by increas-
ing
any one or more of L
RCF
, L
CIC5
, or L
CIC2
within their normal
limits. Achieving a larger L by increasing L
RCF
instead of L
CIC5
or L
CIC2
will relieves the DMEM restriction as well.
In a UMTS example, N
TSP
= 4, f
CLK
= 76.8 MHz, and f
IN
=
3.84 MHz, resulting in L = 80. Factoring L into L
RCF
= 10,
L
CIC
= 8, and L
CIC2
= 1 results in a maximum N
RCF
= 40 due to
the time restriction. Figure 37 shows an example RCF impulse
response which has a frequency response as shown in Figure 38
from 0 Hz to 7.68 MHz (f
IN
L
RCF
/N
TSP
). The composite RCF
and CIC frequency response is shown in Figure 38, on the same
frequency scale. This figure demonstrates a good approximation
to a root-raised-cosine with a roll-off factor of 0.22, a passband
ripple of 0.1 dB, and a stopband ripple better than
–
70 dB until
the lobe of the first image which peaks at
–
60 dB about 7.68 MHz
from the carrier center. This lobe could be reduced by shifting
more of the interpolation towards the RCF, but that would
sacrifice near in performance. As shown, the first image can be
easily rejected by an analog filter further up the signal path.
Scaling must be considered as normal with an interpolation
factor of L, to guarantee no overflow in the RCF, CIC, or NCOs.
The output level at the summation port should be calculated
using an interpolation factor of L/N
TSP
.
Programming Multiple TSPs
Configuring the TSPs for de-interleaved operation is straight
forward. All the Channel Registers and the CMEM of each TSP
are programmed identically, except the Start Hold-Off Counters
and NCO Phase Offset.
In order to separate the input timing to each TSP, the Hold-Off
Counters must be used to start each TSP successively in response
to a common Start SYNC. The Start SYNC may originate from
the SYNC pin or the MicroPort. Each subsequent TSP must have
a Hold-Off Counter value L/N
TSP
larger than its predecessor
’
s.
If the TSPs are located on cascaded
AD6623s, the Hold-Off
Counters of the upstream device should
be incremented by an
additional one.
In the UMTS example, L = 80 and N
TSP
= 4, so to respond as
quickly as possible to a Start SYNC, the Hold-Off Counter
values should be 1, 21, 41, and 61.
Driving Multiple TSP Serial Ports
When configured properly, the AD6623 will drive each SDFO
out of phase. Each new piece of data should be driven only into
the TSP that pulses its SDFO pin at that time.
In the UMTS example in Figure 35, L = 80 and N
TSP
= 4, so
each serial port need only accept every fourth input sample.
Each serial port is shifting at peak capacity, so sample 1, 2, and
3 begin shifting into Serial Ports B, C, and D before sample 0 is
completed into Serial Port A.
SDFOA
SDFOB
SDFOC
SDFOD
0
4
1
5
2
7
6
3
Figure 35. UMTS Example
RAM
COEF
FILTER
CIC
NCO
SUMMATION
BLOCK
CIC
NCO
CIC
NCO
CIC
NCO
DATA
RE-FORMATTER
DAC
RAM
COEF
FILTER
RAM
COEF
FILTER
RAM
COEF
FILTER
76.8 MSAMPLES/SEC
76.8MSPS
76.8MSPS
76.8MSPS
76.8MSPS
9.6MSPS
9.6MSPS
9.6MSPS
9.6MSPS
0.96
MCPS
0.96
MCPS
0.96
MCPS
0.96
MCPS
3.84 MCPS
32
32
32
32
32
I
Q
I
Q
I
Q
I
Q
COMLEX SIGNAL 32 BITS (16, I, 16 Q)
REAL OR IMAGINARY SIGNAL
Figure 36. Summation Block
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AD6623PCB | 4-Channel, 104 MSPS Digital Transmit Signal Processor TSP |
| AD6624AS | Four-Channel, 80 MSPS Digital Receive Signal Processor (RSP) |
| AD6624A | Four-Channel, 100 MSPS Digital Receive Signal Processor (RSP) |
| AD6624AABC | Four-Channel, 100 MSPS Digital Receive Signal Processor (RSP) |
| AD6630AR-REEL | Differential, Low Noise IF Gain Block with Output Clamping |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD6623ASZ | 功能描述:IC TSP 4CHAN 104MSPS 128MQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 專用 系列:- 特色產(chǎn)品:NXP - I2C Interface 標準包裝:1 系列:- 應用:2 通道 I²C 多路復用器 接口:I²C，SM 總線 電源電壓:2.3 V ~ 5.5 V 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應商設(shè)備封裝:16-TSSOP 包裝:剪切帶 (CT) 安裝類型:表面貼裝 產(chǎn)品目錄頁面:825 (CN2011-ZH PDF) 其它名稱:568-1854-1 |
| AD6623BC/PCB | 制造商:AD 制造商全稱:Analog Devices 功能描述:4-Channel, 104 MSPS Digital Transmit Signal Processor TSP |
| AD6623PCB | 制造商:AD 制造商全稱:Analog Devices 功能描述:4-Channel, 104 MSPS Digital Transmit Signal Processor TSP |
| AD6623S/PCB | 制造商:Analog Devices 功能描述:4-CH, 104 MSPS DGTL TRANSMIT SGNL PROCESSOR (TSP) 28SOIC - Bulk |
| AD6624 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Four-Channel, 80 MSPS Digital Receive Signal Processor (RSP) |
發(fā)布緊急采購，3分鐘左右您將得到回復。