參數(shù)資料
型號(hào)： AD6600PCB
廠商： Analog Devices, Inc.
英文描述： Dual Channel, Gain-Ranging ADC with RSSI
中文描述： 雙通道，增益測(cè)距型ADC的RSSI
文件頁(yè)數(shù)： 23/24頁(yè)
文件大?。?/td> 303K
代理商： AD6600PCB
REV. 0
AD6600
–23–
Connecting the AD6600 with the AD6620
The AD6600 interfaces directly to the AD6620 Digital Receive
Signal Processor as shown in Figure 31. No additional external
components are required. Note that the layout requirements dis-
cussed previously do apply and deviations can result in degraded
performance. The digital outputs of the AD6600 must connect
directly to the AD6620 inputs with no additional fanout. Addi-
tional loading on the outputs will compromise timing performance.
AD6600
AD6620
(MSB) D10
D3
D2
D1
(LSB) D0
D9
D8
D7
D6
D5
D4
IN15
IN14
IN13
IN12
IN11
IN10
IN9
IN8
IN7
IN6
IN5
IN4
IN3
IN2
IN1
IN0
EXP2
EXP1
EXP0
A/B
CLK
RSSI2
RSSI1
RSSI0
AB_OUT
CLK2
ENC
ENC
Figure 31. AD6600/AD6620 Connections
Figure 32 shows the timing details between the AD6600 and the
AD6620. On Clock 1, D[10:0], RSSI[2:0], and AB_OUT are
captured by the AD6620. Since AB_OUT has changed state from
the previous clock, the D[10:0] and RSSI[2:0] are processed by
the AD6620. This clock allows adequate setup and hold time
for AB_OUT, D[10:0], and RSSI[2:0] to be captured by the
AD6620.
On Clock2, D[10:0], RSSI[2:0], and AB_OUT are captured
by the AD6620. Since AB_OUT has not changed from the
previous clock, the D[10:0] and RSSI[2:0] are ignored by the
AD6620. This clock is concerned only with the AB_OUT setup-
and-hold time.
CLK2
D [10:0]
RSSI [2:0]
AB_OUT
38.5
38.5
3.0
16.5
7.0
3.0
16.5
12.5
CLOCK1
CLOCK2
Figure 32. AD6600 to AD6620 Timing at 13 MSPS
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