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參數(shù)資料
| 型號： | AD6435 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 通信及網(wǎng)絡 |
| 英文描述： | ADSL（Asymmetric digital Subscriber Line）Chipset(非對稱數(shù)字用戶鏈路芯片組) |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, PQFP128 |
| 封裝： | PLASTIC, TQFP-128 |
| 文件頁數(shù)： | 6/12頁 |
| 文件大?。?/td> | 89K |
| 代理商： | AD6435 |
AD6435
–6–
REV. 0
INT RODUC T ION
T he AD6435 is the interface chip in the AD20msp910 ADSL
chipset, connecting the core transceiver functions to the external
system. T he other portions within the AD20msp910 chipset are
the AD6436 (which connects to the AD6435 and is responsible
for the core DMT signal processing), the AD6437 analog front-
end IC, the AD816 driver/receiver and ADT SP2183, which is
used as the system control processor. An object code licence for
all modem software is supplied with the AD20msp910 chipset.
T he AD6435 implements a generic interface, with straightfor-
ward synchronous clock and data streams corresponding to
simplex and duplex bearer channels. T hese can be considered as
the AS0 (simplex) and LS0 (duplex) streams as per the standard,
but can run at any rate; the “duplex” channel can be treated as
two independent streams, one up and one down. T his implemen-
tation is a simplified variant of that described in ANSI T 1.413.
It is easy to use this structure to connect to the rest of the sys-
tem, or to external devices, such as framers or dedicated ICs for
particular protocols. Variants of the AD6435 with support for
specific functions or interfaces (e.g., AT M, Ethernet) are under
development.
T here are two main blocks within the AD6435:
T he digital processing section (Digital Interface Area or
“DIA”), which is responsible for error correction, scram-
bling, interleaving, AOC and control operations. T his is
based on the earlier AD6442 device. T his is a highly pro-
grammable system, whose operation is not restricted to the
operating modes as defined in ANSI T 1.413, but which
could be used in variety of systems. T he DIA supports the
following codeword cases:
a. One codeword per frame in the fact and/or interleaved
data portion of a frame.
b. Multiple codewords per frame in the fast and/or inter-
leaved data portion, providing the codeword length evenly
divides into the output (DME) frame length.
c. Multiple frames per codeword on the interleaved portion
of the frame only, up to 20 frames per codeword. T he
number of checkbytes must be an integer multiple of the
number of frames in the codeword.
d. Codewords may span superframes.
T he interface block (T ransceiver Interface and Control Logic
or “T ICL”), which handles the framing, signal buffering and
data retiming functions required to support clean synchronous
data streams. (T his essentially corresponds to the transmission
convergence layer of a stack.) As some designs may not require
the T ICL block, there is a bypass mode, in which this block is
powered down and there is access to the unformatted/unframed
data stream from the DIA.
T his data sheet gives a user’s description of the AD6435. It
describes functionality and interfacing, but does not give any
details of the internal structure. For details of the internal struc-
ture, see the AD6435 User’s Manual, available on request.
When used as part of the AD20msp910 ADSL chipset, the
internal functionality is under the control of the firmware sup-
plied with the ADT SP2183, and the Messaging Protocol (MP)
implemented there. T his protocol supplies a hardware-neutral
method of controlling the operation of the ADSL chipset, which
will be compatible between different hardware implementations.
T he AD6435 can implement rate adaptive ADSL (RADSL).
T his is under the control of the MP, and several different modes
are supported.
T he absolute maximum data rate of the AD6435 is 12 Mbps
downstream, and 4 Mbps upstream. However, the rate depends
primarily on the channel conditions, and these rates will not be
achieved on real loops, with attenuation and crosstalk.
RX_BUF
RFS
RX_FR
RX_SPFR
RX_SPFRI
TX_BUF
TX_FR
TFS
TX_SPFR
MCLK_OUT
DUPLX_RX
DUPLX_CLKO
DUPLX_CLKI
DUPLX_TX
SIMPLX_CLKI
SIMPLX_TX
SIMPLX_CLKO
SIMPLX_RX
N
N
N
D
D
A
N
R
M
T
TX_RX_SCLK
TX_SDATA
TX_DREQ
TX_FRM
TX_BS
RX_FRM
RX_BS
RX_SDATA
RX_DREQ
M_A(14:0)
M_D(7:0)
NM_WE
NM_OE
DTIR
ADTSP2183 INTERFACE
D
I
T
D
CONTROL INTERFACE
Figure 1. Functional Diagram
INT E RFACE S
T he standard interface is a very straightforward buffered and
demultiplexed synchronous connection. It is physically the same
at both AT U-R and AT U-C, and presents four channels—
simplex in and out, duplex in and out—with just two signals per
connection, clock and data (obviously, only three of these chan-
nels can be used at an end; with the AT U-C using simplex_in
and the AT U-R simplex_out). T hese streams are independent
and can be used asynchronously of one another. No framing
signals are provided.
T he “duplex” stream can be used as a true duplex carrier (same
rates upstream and downstream) or the two may be independent
(i.e., the chipset has two simplex downstream paths, one fast
and one slower, and one simplex upstream).
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