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參數(shù)資料
| 型號： | AD6435 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 通信及網(wǎng)絡 |
| 英文描述： | ADSL（Asymmetric digital Subscriber Line）Chipset(非對稱數(shù)字用戶鏈路芯片組) |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, PQFP128 |
| 封裝： | PLASTIC, TQFP-128 |
| 文件頁數(shù)： | 4/12頁 |
| 文件大小： | 89K |
| 代理商： | AD6435 |
AD6435
–4–
REV. 0
PIN FUNCT ION DE SCRIPT IONS
Pin No.
Pin Name
T ype
Description
1–2
3
4
5
6
7
8
9
10
11
12
13
14
D1, D0
T EST 4
SIMPLX _T X
SIMPLX _CLK I
SIMPLX _CLK O
VDD1
GND1
SIMPLX _RX
DUPLX _T X
DUPLX _CLK I
DUPLX _CLK O
DUPLX _RX
RX _BUF
I/O
Input
Input
Input
Output
Supply
Supply
Output
Input
Input
Output
Output
Output
16-Bit Data Bus for DSP Port. See also 111:114, 117:124, 127:128.
T ie to Ground T hrough a 10 k
Resistor.
Input Downstream Data at CO. Pin not used at RT .
Input Clock at CO for Downstream Data. Pin is not used at RT .
Recovered Downstream Clock at RT . Pin not used at CO.
3.3 V.
Ground.
Received Downstream Data at RT . Pin not used at CO.
Input Duplex Data.
Input Duplex Clock.
Recovered Duplex Clock.
Received Duplex Data Stream.
T ICL Bypass—RX Data Buffer. If T CIL is not used, this pin must have a
pull-up resistor.
3.3 V.
Ground.
T ICL Bypass—RX Byte Sync.
T ICL Bypass—RX Frame Sync. 10 k
to Ground.
T ICL Bypass—T ICL Superframe Sync.
T ICL Bypass—RX Interleaved Superframe Sync.
T ICL Bypass—T X Data Buffer.
T ICL Bypass—T X Byte Sync.
Ground.
3.3 V.
T ICL Bypass—T X Frame Sync.
T ICL Bypass—T X Superframe Sync.
T ICL Bypass—Output MCLK .
No Connection.
No Connection.
Mode Pin, 1 = RT Mode, 0 = CO Mode.
Ground.
3.3 V.
No Connect.
PLL Analog Ground.
PLL Analog Power.
T ie to Ground T hrough a 30 k
Resistor.
No Connect.
T ie to Ground T hrough a 10 k
Resistor.
No Connection.
3.3 V.
Ground.
Data for Interleave Ram.
3.3 V.
Ground.
Address Bus for Interleave Ram. See also Pins 60–66.
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33, 34
35
36
37
38
39
40
41
42
43–50
51
52
53–60
VDD2
GND2
RFS
RX _FR
RX _SPFR
RX _SPFRI
T X _BUF
T FS
GND3
VDD3
T X _FR
T X _SPFR
MCLK _OUT
T EST 0
T EST 1
RT _NCO
GND4
VDD4
NC
PLL_GND
PLL_VDD
PLL_RBIAS
NC
T EST 2
T EST 3
VDD5
GND5
M_D7–0
VDD6
GND6
M_A0–7
Supply
Supply
Output
Output
Output
Output
Input
Output
Supply
Supply
Output
Output
Output
Supply
Supply
Input
T hree-State
Supply
Supply
I/O
Supply
Supply
Output
PIN DE SCRIPT ION
T he AD6435 contains 91 signal pins, 33 output pins, 35 input pins, and 24 bidirectional pins. T here are also 5 test pins and
28 digital supply pins, 2 analog supply pins, and 1 PLL bias pin for the PLL.
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