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參數(shù)資料
| 型號： | AD608 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Low Power Mixer/Limiter/RSSI 3 V Receiver IF Subsystem(低功耗混合器/Limiter/RSSI 3V接收器IF子系統(tǒng)) |
| 中文描述： | 低功耗混合機(jī)/限制器/ RSSI的3 V接收機(jī)中頻子系統(tǒng)（低功耗混合器/限幅/ RSSI的3V的接收器中頻子系統(tǒng)） |
| 文件頁數(shù)： | 8/12頁 |
| 文件大?。?/td> | 201K |
| 代理商： | AD608 |
REV. B
–8–
AD608
IF Filter T erminations
T he AD608 was designed to drive a parallel-terminated 10.7 MHz
bandpass filter with a 330
impedance. With a 330
parallel-
terminated filter, pin MX OP sees a 165
termination and the
gain is nominally 24 dB. Other filter impedances and gains can
be accommodated by either accepting an increase or decrease in
gain in proportion to the filter impedance or by keeping the im-
pedance seen by MX OP a nominal 165
(by using resistive di-
viders or matching networks). Figure 21 shows a simple resistive
voltage divider for matching an assortment of filter impedances,
and T able II lists component values.
T he Logarithmic IF Amplifier
T he logarithmic IF amplifier consists of five amplifier stages
of 16 dB gain each, plus a final limiter. T he IF bandwidth is
30 MHz (–1 dB) and the limiting gain is 110 dB. T he phase
skew is
±
3
°
from –75 dBm to +5 dBm (approximately 111
μ
V
p-p to 1.1 V p-p). T he limiter output impedance is 200
and the limiter’s output drive is
±
200 mV (400 mV p-p) into a
5 k
load. In the absence of an input signal, the limiter’s output
will limit on noise fluctuations, which produces an output that
continues to swing 400 mV p-p but with random zero crossings.
Offset Feedback Loop
Because the logarithmic amplifier is dc coupled and has more
than 110 dB of gain from the input to the limiter output, a dc
offset at its input of even a few
μ
V would cause the output to
saturate. T hus, the AD608 uses a low frequency feedback loop
to null out the input offset. Referring to Figure 21, the loop
consists of a current source driven by the limiter, which sends
50
μ
A current pulses to pin FDBK . T he pulses are low pass
filtered by a
π
-network consisting of C1, R4, and C5. T he
smoothed dc voltage that results is subtracted from the input to
the IF amplifier at pin IFLO. Because this is a high gain ampli-
fier with a feedback loop, care should be taken in layout and
component values to prevent oscillation. Recommended values
for the common IFs of 450 kHz, 455 kHz, 6.5 MHz, and
10.7 MHz are listed in T able II.
24dB MIXER GAIN
110dB LIMITER GAIN
90dB RSSI
BIAS
MXOP
MIXER
BPF
DRIVER
VMID
LO
PREAMP
AD608
RFHI
RFLO
IFHI
IFLO
LMOP
VPS2
RSSI
FDBK
COM3
FINAL
LIMITER
100nF
C5
R1
±
50
μ
A
BANDPASS
FILTER
MID-SUPPLY
IF BIAS
6
5
7
8
10
9
13
14
12
15
11
1
2
3
4
16
PRUP
VPS1 COM1
COM2
LOHI
12dB NOMINAL
INSERTION LOSS
(ASSUMES 6dB IN FILTER)
5-STAGE IF AMPLIFIER
(16dB PER STAGE)
7 FULL-WAVE
RECTIFIER CELLS
≈
2MHz
LPF
≈
R4
C1
+5V
C1
1
μ
F
LO INPUT
–16dBm
C2
100pF
CMOS
LOGIC
INPUT
R2
R3
47k
Figure 21. Applications Diagram for Common IFs and Filter Impedances
T able II. AD608 Filter T ermination and Offset-Null Feedback Loop Resistor and Capacitor Values for Common IFs
Filter
Impedance
Filter T ermination Resistor
Values
1
for 24 dB of Mixer Gain
Offset Null
Feedback Loop Values
IF
R1
174
174
178
330
R2
1330
1330
825
0
R3
1500
1500
1000
330
R4
1000
1000
100
100
C 1
200 nF
200 nF
18 nF
18 nF
C 5
100 nF
100 nF
10 nF
10 nF
450 kHz
2
455 kHz
6.5 MHz
10.7 MHz
1500
1500
1000
330
NOT ES
1
Resistor values were calculated so that R1 + R2 = Z
and R1
i
(R2+Z
) = 165
.
2
Operation at IFs of 450 kHz and 455 kHz requires an external low pass filter with at least one pole at a cutoff frequency of 90 kHz (a decade below the ripple
at 900 kHz).
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