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參數(shù)資料
| 型號(hào)： | AD607ARS |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 無繩電話/電話 |
| 英文描述： | Low Power Mixer/AGC/RSSI 3 V Receiver IF Subsystem |
| 中文描述： | TELECOM, CELLULAR, BASEBAND CIRCUIT, PDSO20 |
| 封裝： | PLASTIC, MO-150AE, SSOP-20 |
| 文件頁數(shù)： | 4/24頁 |
| 文件大?。?/td> | 510K |
| 代理商： | AD607ARS |
REV. 0
–4–
AD607
PIN DESCRIPTION
Pin
Mnemonic
Reads
Function
1
FDIN
Frequency Detector Input
PLL input for I/Q demodulator quadrature oscillator,
±
400 mV
drive required from external oscillator. Must be biased at V
P
/2.
Supply common for RF front end and main bias.
3 V/5 V CMOS compatible power-up control; logical high =
powered-up; max input level = VPS1 = VPS2.
LO input, ac coupled
±
54 mV LO input required (–16 dBm for
50
input termination).
Usually connected to ac ground.
AC coupled,
±
56 mV, max RF input for linear operation.
High impedance input, typically 1.5 V, sets gain scaling.
High impedance, single-sided current output,
±
1.3 V max voltage
output (
±
6 mA max current output).
Output of the midsupply bias generator (VMID = VPOS/2).
AC coupled IF input,
±
56 mV max input for linear operation.
Reference node for IF input; auto-offset null.
High impedance input, 0 V–2 V using 3 V supply, max gain at
V = 0. RSSI Output when using Internal AGC Detector; RSSI
voltage is across AGC Capacitor connected to this pin.
Supply common for IF stages and demodulator.
Low impedance, single-sided voltage output, +5 dBm (
±
560 mV)
max.
Signal input to I and Q demodulators
±
150 mV max input at IF
> 3 MHz for linear operation;
±
75 mV max input at IF < 3 MHz
for linear operation. Must be biased at V
P
/2.
Supply to high-level IF, PLL, and demodulators.
Low impedance Q baseband output
±
1.23 V full scale in 20 k
min load; ac coupled.
Low impedance I baseband output;
±
1.23 V full scale in 20 k
min load; ac coupled.
Series RC PLL Loop filter, connected to ground.
Supply to mixer, low level IF, PLL, and gain control.
2
3
COM1
PRUP
Common #1
Power-Up Input
4
LOIP
Local Oscillator Input
5
6
7
8
RFLO
RFHI
GREF
MXOP
RF “Low” Input
RF “High” Input
Gain Reference Input
Mixer Output
9
10
11
12
VMID
IFHI
IFLO
GAIN/RSSI
Midsupply Bias Voltage
IF “High” Input
IF “Low” Voltage
Gain Control Input/RSSI Output
13
14
COM2
IFOP
Common #2
IF Output
15
DMIP
Demodulator Input
16
17
VPS2
QOUT
VPOS Supply #2
Quadrature Output
18
IOUT
In-Phase Output
19
20
FLTR
VPS1
PLL Loop Filter
VPOS Supply #1
PIN CONNECTION
20-Pin SSOP (RS-20)
14
13
12
11
17
16
15
20
19
18
10
9
8
1
2
3
4
7
6
5
TOP VIEW
(Not to Scale)
AD607
FDIN
QOUT
IOUT
FLTR
VPS1
COM1
PRUP
LOIP
IFOP
DMIP
VPS2
RFLO
RFHI
GREF
MXOP
VMID
IFHI
IFLO
GAIN/RS
COM2
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