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參數(shù)資料
| 型號： | AD602JRZ |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 模擬信號調(diào)理 |
| 英文描述： | Dual, Low Noise, Wideband Variable Gain Amplifiers |
| 中文描述： | SPECIALTY ANALOG CIRCUIT, PDSO16 |
| 封裝： | LEAD FREE, MS-013AA, SOIC-16 |
| 文件頁數(shù)： | 23/28頁 |
| 文件大?。?/td> | 432K |
| 代理商： | AD602JRZ |
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AD600/AD602
Rev. E | Page 23 of 28
2.0
–2.0
0.5
1.0
1.5
–1.5
–1.0
–0.5
G
–0.1
0.1
0
1μ
10μ
10
1
100m
10m
1m
100μ
INPUT SIGNAL (V rms)
0
Figure 49. Gain Error for Figure 41 Without the 2 dB Offset Modification
2.0
–2.0
0.5
1.0
1.5
–1.5
–1.0
–0.5
G
–0.1
0.1
0
1μ
10μ
10
1
100m
10m
1m
100μ
INPUT SIGNAL (V rms)
0
Figure 50. Adding the 2 dB Offsets Improves the Linearization
The maximum gain of this circuit is 120 dB. If no filtering was
used, the noise spectral density of the AD600 (1.4 nV/√Hz)
would amount to an input noise of 8.28 μV rms in the full
bandwidth (35 MHz). At a gain of one million, the output noise
would dominate. Consequently, some reduction of bandwidth is
mandatory, and in the circuit of Figure 47, it is due mostly to a
single-pole, low-pass filter R5/C3, which provides a 3 dB
frequency of 458 kHz, which reduces the worst-case output
noise (at V
AGC
) to about 100 mV rms at a gain of 100 dB. Of
course, the bandwidth (and therefore the output noise) could be
further reduced, for example, in audio applications, merely by
increasing C3. The value chosen for this application is optimal
in minimizing the error in the V
LOG
output for small input signals.
The AD600 is dc-coupled, but even miniscule offset voltages at
the input would overload the output at high gains; thus, high-
pass filtering is also needed. To provide operation at low
frequencies, two simple 0s at about 12 Hz are provided by
R1/C1 and R4/C2; op amp sections U3A and U3B (
AD713
)
are used to provide impedance buffering, because the input
resistance of the AD600 is only 100 Ω. A further 0 at 12 Hz is
provided by C4 and the 6.7 kΩ input resistance of the AD636
rms converter.
The rms value of V
LOG
is generated at Pin 8 of the AD636; the
averaging time for this process is determined by C5, and the
value shown results in less than 1% rms error at 20 Hz. The
slowly varying V rms is compared with a fixed reference of
316 mV, derived from the positive supply by R10/R11. Any
difference between these two voltages is integrated in C6, in
conjunction with Op Amp U3C, the output of which is V
LOG
. A
fraction of this voltage, determined by R12 and R13, is returned
to the gain control inputs of all AD600 sections. An increase in
V
LOG
lowers the gain because this voltage is connected to the
inverting polarity control inputs.
In this case, the gains of all three VCA sections are being varied
simultaneously, so the scaling is not 32 dB/V but 96 dB/V or
10.42 mV/dB. The fraction of V
LOG
required to set its scaling to
50 mV/dB is therefore 10.42/50 or 0.208. The resulting full-
scale range of V
LOG
is nominally ±2.5 V. This scaling allows the
circuit to operate from ±5 V supplies.
Optionally, the scaling can be altered to 100 mV/dB, which
would be more easily interpreted when V
LOG
is displayed on a
DVM by increasing R12 to 25.5 kΩ. The full-scale output of
±5 V then requires the use of supply voltages of at least ±7.5 V.
A simple attenuator of 16.6 ± 1.25 dB is formed by R2/R3
and the 100 Ω input resistance of the AD600. This allows the
reference level of the decibel output to be precisely set to 0 for
an input of 3.16 mV rms, and thus center the 100 dB range
between 10 μV and 1 V. In many applications, R2/R3 can be
replaced by a fixed resistor of 590 Ω. For example, in AGC
applications, neither the slope nor the intercept of the
logarithmic output is important.
A few additional components (R14 to R16 and Q1) improve the
accuracy of V
LOG
at the top end of the signal range (that is, for
small gains). The gain starts rolling off when the input to the
first amplifier, U1A, reaches 0 dB. To compensate for this
nonlinearity, Q1 turns on at V
LOG
~ 1.5 V and increases the
feedback to the control inputs of the AD600s, thereby needing a
smaller voltage at V
LOG
to maintain the input to the AD636 to
the setpoint of 316 mV rms.
A 120 dB RMS/AGC SYSTEM WITH OPTIMAL SNR
(SEQUENTIAL GAIN)
In the last case, all gains were adjusted simultaneously, resulting
in an output SNR that is always less than optimal. The use of
sequential gain control results in a major improvement in SNR,
with only a slight penalty in the accuracy of V
LOG
, and no
penalty in the stabilization accuracy of V
AGC
. The idea is to
increase the gain of the earlier stages first (as the signal level
decreases) and maintain the highest SNR throughout the
amplifier chain. This can be easily achieved with the AD600
because its gain is accurate even when the control input is
overdriven. That is, each gain control window of 1.25 V is
used fully before moving to the next amplifier to the right.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD602JRZ-R7 | 功能描述:IC AMP VGA DUAL LN 50MA 16SOIC RoHS:是 類別:集成電路 (IC) >> Linear - Amplifiers - Instrumentation 系列:X-AMP® 標(biāo)準(zhǔn)包裝:2,500 系列:Excalibur™ 放大器類型:J-FET 電路數(shù):1 輸出類型:- 轉(zhuǎn)換速率:45 V/µs 增益帶寬積:10MHz -3db帶寬:- 電流 - 輸入偏壓:20pA 電壓 - 輸入偏移:490µV 電流 - 電源:1.7mA 電流 - 輸出 / 通道:48mA 電壓 - 電源，單路/雙路(±):4.5 V ~ 38 V，±2.25 V ~ 19 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:8-SOIC（0.154"，3.90mm 寬） 供應(yīng)商設(shè)備封裝:8-SOIC 包裝:帶卷 (TR) |
| AD602JRZ-RL | 功能描述:IC AMP VGA DUAL LN 50MA 16SOIC RoHS:是 類別:集成電路 (IC) >> Linear - Amplifiers - Instrumentation 系列:X-AMP® 標(biāo)準(zhǔn)包裝:2,500 系列:Excalibur™ 放大器類型:J-FET 電路數(shù):1 輸出類型:- 轉(zhuǎn)換速率:45 V/µs 增益帶寬積:10MHz -3db帶寬:- 電流 - 輸入偏壓:20pA 電壓 - 輸入偏移:490µV 電流 - 電源:1.7mA 電流 - 輸出 / 通道:48mA 電壓 - 電源，單路/雙路(±):4.5 V ~ 38 V，±2.25 V ~ 19 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:8-SOIC（0.154"，3.90mm 寬） 供應(yīng)商設(shè)備封裝:8-SOIC 包裝:帶卷 (TR) |
| AD602SQ/883B | 制造商:Rochester Electronics LLC 功能描述:VARIABLE GAIN AMP IC - Bulk |
| AD603 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Low Noise, 90 MHz Variable Gain Amplifier |
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