參數(shù)資料
型號(hào): AD602JRZ-RL
廠商: ANALOG DEVICES INC
元件分類: 模擬信號(hào)調(diào)理
英文描述: Dual, Low Noise, Wideband Variable Gain Amplifiers
中文描述: SPECIALTY ANALOG CIRCUIT, PDSO16
封裝: LEAD FREE, MS-013AA, SOIC-16
文件頁數(shù): 22/28頁
文件大?。?/td> 432K
代理商: AD602JRZ-RL
AD600/AD602
Rev. E | Page 22 of 28
C1HI
A1CM
A1OP
VPOS
VNEG
A2OP
A2CM
C2HI
C1LO
A1HI
A1LO
GAT1
GAT2
A2LO
A2HI
C2LO
+5V
DEC
–5V
DEC
–5V
DEC
NC
NC
NC
NC
NC
NC
C5
22μF
+5V DEC
R11
46.4k
R10
3.16k
U3C
INPUT
1V rms
MAX
(SINEWAVE)
U3A
1/4
AD713
C2
0.1μF
NC = NO CONNECT
R6
10k
R7
127
R8
127
R9
10k
+5V
–5V
C1HI
A1CM
A1OP
VPOS
VNEG
A2OP
A2CM
C2HI
C1LO
A1HI
A1LO
GAT1
GAT2
A2LO
A2HI
C2LO
C1
0.1μF
C3
220pF
R4
133k
R5
1.58k
R2
487
R3
200
R1
133k
–2dB
–62.5mV
0dB
+2dB
+62.5mV
C6
4.7μF
+316.2mV
R16
6.65k
R15
19.6k
+5V DEC
R13
3.01k
R12
11.3k
R14
301k
Q1
2N3906
1
2
3
4
5
6
7
14
13
12
11
10
9
8
U4
AD636
VINP
VNEG
CAVG
VLOG
BFOP
BFIN
VPOS
COMM
LDLO
V
RMS
FB
FB
+5V
–5V
+5V
DEC
–5V
DEC
0.1μF
0.1μF
POWER SUPPLY
DECOUPLING
NETWORK
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
REF
A1
A2
+
+
U1 AD600
U3B
1/4
AD713
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
REF
A1
A2
+
+
U2 AD600
V
OUT
+5V
DEC
–5V
DEC
1/4
AD713
V
LOG
C4
2μF
0
Figure 47. RMS Responding AGC Circuit with 100 dB Dynamic Range
A 100 dB RMS/AGC SYSTEM WITH MINIMAL GAIN
ERROR (PARALLEL GAIN WITH OFFSET)
Figure 47 shows an rms-responding AGC circuit that can be
used equally well as an accurate measurement system. It accepts
inputs of 10 μV to 1 V rms (100 dBV to 0 dBV) with generous
overrange. Figure 48 shows the logarithmic output, V
LOG
, which
is accurately scaled 1 V per decade, that is, 50 mV/dB, with an
intercept (V
LOG
= 0) at 3.16 mV rms (50 dBV). Gain offsets of
±2 dB were introduced between the amplifiers, provided by the
±62.5 mV introduced by R6 to R9. These offsets cancel a small
gain ripple that arises in the X-AMP from its finite interpolation
error, which has a period of 18 dB in the individual VCA
sections. The gain ripple of all three amplifier sections without
this offset (in which case, the gain errors simply add) is shown
in Figure 49; it is still a remarkably low ±0.25 dB over the
108 dB range from 6 μV to 1.5 V rms. However, with the gain
offsets connected, the gain linearity remains under ±0.1 dB over
the specified 100 dB range (see Figure 50).
5
3
–5
10μ
10
1
100m
10m
1m
100μ
4
2
0
1
–1
–3
–2
–4
INPUT SIGNAL (V rms)
L
0
Figure 48. V
LOG
Plotted vs. V
IN
for Figure 47’s Circuit Showing 120 dB AGC Range
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