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參數(shù)資料
| 型號： | AD602JRZ-R7 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 模擬信號調(diào)理 |
| 英文描述： | Dual, Low Noise, Wideband Variable Gain Amplifiers |
| 中文描述： | SPECIALTY ANALOG CIRCUIT, PDSO16 |
| 封裝： | LEAD FREE, MS-013AA, SOIC-16 |
| 文件頁數(shù)： | 21/28頁 |
| 文件大?。?/td> | 432K |
| 代理商： | AD602JRZ-R7 |
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AD600/AD602
This system can, of course, be used as an AGC amplifier in
which the rms value of the input is leveled. Figure 43 shows the
decibel output voltage. More revealing is Figure 44, which
shows that the deviation from the ideal output predicted by
Equation 1 over the input range 80 μV to 500 mV rms is within
±0.5 dB, and within ±1 dB for the 80 dB range from 80 μV to
800 mV. By suitable choice of the input attenuator R1 + R2, this
can be centered to cover any range from a low of 25 mV to
250 mV to a high of 1 mV to 10 V, with appropriate correction
to the value of V
REF
. Note that V
SCALE
is not affected by the
changes in the range. The gain ripple of ±0.2 dB seen in this
curve is the result of the finite interpolation error of the
X-AMP. Note that it occurs with a periodicity of 12 dB, twice
the separation between the tap points (because of the two
cascaded stages).
Rev. E | Page 21 of 28
5
0
–5
1
2
3
4
–4
–3
–2
–1
10μ
100μ
10
1
100m
10m
1m
INPUT SIGNAL (V rms)
V
O
0
Figure 43. The dB Output of Figure 41’s Circuit is Linear over an 80 dB Range
2.5
0
–2.5
0.5
1.0
1.5
2.0
–2.0
–1.5
–1.0
–0.5
O
10μ
100μ
10
1
100m
10m
1m
INPUT SIGNAL (V rms)
0
Figure 44. Data from Figure 42 Presented as the Deviation
from the Ideal Output Given in Equation 4
This ripple can be canceled whenever the X-AMP stages are
cascaded by introducing a 3 dB offset between the two pairs of
control voltages. A simple means to achieve this is shown in
Figure 45: the voltages at C1HI and C2HI are split by
±46.875 mV, or ±1.5 dB. Alternatively, either one of these pins
can be individually offset by 3 dB and a 1.5 dB gain adjustment
made at the input attenuator (R1 + R2).
16
15
14
13
12
11
10
9
U1
AD600
C1HI
A1CM
A1OP
VPOS
VNEG
A2OP
A2CM
C2HI
+6V DEC
–6V DEC
C2
2μF
1
2
3
4
5
6
7
VINP
VNEG
CAVG
VLOG
BFOP
BFIN
U2
AD636
NC
NC
NC
–6V DEC
–46.875mV
NC = NO CONNECT
10k
10k
+6V
DEC
–6V
DEC
78.7
78.7
3dB OFFSET
MODIFICATION
+46.875mV
0
Figure 45. Reducing the Gain Error Ripple
The error curve shown in Figure 46 demonstrates that over the
central portion of the range the output voltage can be maintained
close to the ideal value. The penalty for this modification is the
higher errors at the extremities of the range. The next two
applications show how three amplifier sections can be cascaded
to extend the nominal conversion range to 120 dB, with the
inclusion of simple LP filters of the type shown in Figure 37.
Very low errors can then be maintained over a 100 dB range.
2.5
0
–2.5
0.5
1.0
1.5
2.0
–2.0
–1.5
–1.0
–0.5
O
10μ
100μ
10
1
100m
10m
1m
INPUT SIGNAL (V rms)
0
Figure 46. Using a 3 dB Offset Network Reduces Ripple
100 dB TO 120 dB RMS RESPONDING CONSTANT
BANDWIDTH AGC SYSTEMS WITH HIGH
ACCURACY dB OUTPUTS
The next two applications double as both AGC amplifiers and
measurement systems. In both, precise gain offsets are used to
achieve either a high gain linearity of ±0.1 dB over the full
100 dB range or the optimal SNR at any gain.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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| AD602JRZ-RL | 功能描述:IC AMP VGA DUAL LN 50MA 16SOIC RoHS:是 類別:集成電路 (IC) >> Linear - Amplifiers - Instrumentation 系列:X-AMP® 標準包裝:2,500 系列:Excalibur™ 放大器類型:J-FET 電路數(shù):1 輸出類型:- 轉(zhuǎn)換速率:45 V/µs 增益帶寬積:10MHz -3db帶寬:- 電流 - 輸入偏壓:20pA 電壓 - 輸入偏移:490µV 電流 - 電源:1.7mA 電流 - 輸出 / 通道:48mA 電壓 - 電源，單路/雙路(±):4.5 V ~ 38 V，±2.25 V ~ 19 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:8-SOIC（0.154"，3.90mm 寬） 供應商設(shè)備封裝:8-SOIC 包裝:帶卷 (TR) |
| AD602SQ/883B | 制造商:Rochester Electronics LLC 功能描述:VARIABLE GAIN AMP IC - Bulk |
| AD603 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Low Noise, 90 MHz Variable Gain Amplifier |
| AD603_05 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Low Noise, 90 MHz Variable Gain Amplifier |
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