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參數(shù)資料
| 型號： | AD5930YRUZ |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 模擬信號調(diào)理 |
| 英文描述： | Programmable Frequency Sweep and Output Burst Waveform Generator |
| 中文描述： | SPECIALTY ANALOG CIRCUIT, PDSO20 |
| 封裝： | LEAD FREE, MO-153AC, TSSOP-20 |
| 文件頁數(shù)： | 19/28頁 |
| 文件大?。?/td> | 505K |
| 代理商： | AD5930YRUZ |
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AD5930
SETTING UP THE FREQUENCY SWEEP
As stated previously in The Frequency Profile section, the
AD5930 requires certain registers to be programmed to enable a
frequency sweep. The following sections discuss these registers
in more detail.
Rev. 0 | Page 19 of 28
Start Frequency (F
START
)
To start a frequency sweep, the user needs to tell the AD5930
what frequency to start sweeping from. This frequency is stored
in a 24-bit register called F
START
. If the user wishes to alter the
entire contents of the F
START
register, two consecutive writes
must be preformed, one to the LSBs and the other to the MSBs.
Note that for an entire write to this register, the Control Bit B24
(D11) should be set to 1 with the LSBs programmed first.
In some applications, the user does not need to alter all 24 bits
of the F
START
register. By setting the Control Bit B24 (D11) to 0,
the 24-bit register operates as two 12-bit registers, one
containing the 12 MSBs and the other containing the 12 LSBs.
This means that the 12 MSBs of the F
START
word can be altered
independently of the 12 LSBs, and vice versa. The addresses of
both the LSBs and the MSBs of this register is given in Table 8.
Table 8. F
START
Register Bits
D15
D14
D13
D12
1
1
0
0
1
1
0
1
Frequency Increments (
f)
The value in the Δf register sets the increment frequency for the
sweep and is added incrementally to the current output frequency.
Note that the increment frequency can be positive or negative,
thereby giving an increasing or decreasing frequency sweep.
D11 to D0
12 LSBs of F
START
<11…0>
12 MSBs of F
START
<23…12>
At the start of a sweep, the frequency contained in the F
START
register is output. Next, the frequency (F
START
+ Δf ) is output.
This is followed by (F
START
+ Δf + Δf) and so on. Multiplying the
Δf value by the number of increments (N
INCR
), and adding it to
the start frequency (F
START
), gives the final frequency in the
sweep. Mathematically this final frequency/stop frequency is
represented by
F
START
+ (N
INCR
× Δf).
The Δf register is a 23-bit register, and requires two 16-bit
writes to be programmed. Table 9 gives the addresses associated
with both the MSB and LSB registers of the Δf word.
Table 9. f Register Bits
D15
0
D14
0
D13
1
D12
0
D11
12 LSBs of
f
<11…0>
0
D10 to D0
Sweep
Direction
N/A
0
0
1
1
11 MSBs of
Δ
f <22…12>
11 MSBs of
Δ
f <22…12>
Positive
Δ
f
(F
START
+
Δ
f)
Negative
f
(F
START
Δ
f)
0
0
1
1
1
Number of Increments (N
INCR
)
An end frequency, or a maximum/minimum frequency before
the sweep changes direction is not required on the AD5930.
Instead, this end frequency is calculated by multiplying the
frequency increment value (Δf) by the number of frequency
steps (N
INCR
), and adding it to/subtracting it from the start
frequency (F
START
), that is, F
START
+ N
INCR
× Δ f. The N
INCR
register
is a 12-bit register, with the address shown in Table 10.
Table 10. N
INCR
Register Bits
D15
D14
D13
D12
0
0
0
1
D11 to D0
12 bits of N
INCR
<11…0>
The number of increments is programmed in binary fashion,
with 000000000010 representing the minimum number of
frequency increments (2 increments), and 111111111111
representing the maximum number of increments (4095).
Table 11. N
INCR
Data Bits
D11
D0
Number of Increments
0000
0000
0010
2 frequency increments. This is the
minimum number of frequency
increments.
0000
0000
0011
3 frequency increments.
0000
0000
0100
4 frequency increments.
…
…
…
…
1111
1111
1110
4094 frequency increments.
1111
1111
1111
4095 frequency increments.
Increment Interval (t
INT
)
The increment interval dictates the duration of the DAC output
signal for each individual frequency of the frequency sweep.
The AD5930 offers the user two choices:
The duration is a multiple of cycles of the output frequency.
The duration is a multiple of MCLK periods.
This is selected by Bit D13 in the t
INT
register as shown in Table 12.
Table 12. t
INT
Register Bits
D15
D14
D13
D12
D11
0
1
0
x
x
D10 to D0
11 bits <10…0>
Fixed number of output
waveform cycles.
11 bits <10…0>
Fixed number of clock
periods.
0
1
1
x
x
Programming of this register is in binary form with the
minimum number being decimal 2. Note in Table 12 that 11
bits, Bit D10 to Bit D0, of the register are available to program
the time interval. As an example, if MCLK = 50 MHz, then each
clock period/base interval is (1/50 MHz) = 20 ns. If each
frequency needs to be output for 100 ns, then <00000000101>
or decimal 5 needs to be programmed to this register. Note that
the AD5930 can output each frequency for a maximum
duration of 211 1 (or 2047) times the increment interval.
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