參數(shù)資料
型號(hào): AD5801
廠商: Analog Devices, Inc.
英文描述: Piezo-Electric Actuator Controller
中文描述: 壓電致動(dòng)器控制器
文件頁數(shù): 6/13頁
文件大?。?/td> 209K
代理商: AD5801
AD5801
Preliminary Technical Data
Rev. 0 | Page 6 of 13
Table 3. I
2
C Serial Interface
Parameter
1
F
SCL
t
1
t
2
t
3
t
4
t
5
t
62
t
7
t
8
t
9
t
10
t
11
C
B3
Limit at T
MIN
, T
MAX
400
2.5
0.6
1.3
0.6
100
0.9
0
0.6
0.6
1.3
300
0
300
0
300
20 + 0.1 C
B
400
Unit
kHz max
μs min
μs min
μs min
μs min
ns min
μs max
μs min
μs min
μs min
μs min
ns max
ns min
ns max
ns min
ns max
ns min
pF max
Description
SCL clock frequency
SCL cycle time
t
HIGH
, SCL high time
t
LOW
, SCL low time
t
HD
,
STA
, start/repeated start condition hold time
t
SU
,
DAT
, data setup time
t
HD
,
DAT
data hold time
t
HD
,
DAT
data hold time
t
SU
,
STA
setup time for repeated start
t
SU
,
STO
stop condition setup time
t
BUF
, bus free time between a stop and a start condition
t
F
, fall time of SDA when transmitting
t
R
, rise time of SCL and SDA when receiving (CMOS compatible)
t
F
, fall time of SDA when transmitting
t
F
, fall time of SDA when receiving (CMOS compatible)
t
F
, fall time of SCL and SDA when receiving
t
F
, fall time of SCL and SDA when transmitting
Capacitive load for each bus line
1
See 2.
2
A master device must provide a hold time of at least 300 ns for the SDA signal (referred to the V
IH
MIN of the SCL signal)
to bridge the undefined region of SCL’s falling edge.
3
C
B
is the total capacitance of one bus line in pF; t
R
and t
F
measured between 0.3 V
DD
and 0.7 V
DD
.
0
SCL
SDA
START
CONDITION
RSTART
CONDITION
CSTOP
t
9
t
3
t
10
t
11
t
4
t
4
t
6
t
2
t
5
t
7
t
8
t
1
Figure2.. I
2
C Interface Timing Diagram
Block Diagram
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