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參數(shù)資料
| 型號： | AD5780ACPZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 14/28頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC VOLT OUT 18BIT 24LFCSP |
| 標準包裝： | 1 |
| 設(shè)置時間： | 2.5µs |
| 位數(shù)： | 18 |
| 數(shù)據(jù)接口： | DSP，MICROWIRE?，QSPI?，串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 電壓電源： | 模擬和數(shù)字，雙 ± |
| 工作溫度： | -40°C ~ 125°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 24-VFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 24-LFCSP-VQ EP（4x5） |
| 包裝： | 托盤 |
| 輸出數(shù)目和類型： | 1 電壓，雙極 |
| 配用： | EVAL-AD5780SDZ-ND - BOARD EVALUATION FOR AD5780 |
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Data Sheet
AD5780
Rev. E | Page 21 of 28
Control Register
The control register controls the mode of operation of the
Clearcode Register
The clearcode register sets the value to which the DAC output is
set when the CLR pin or CLR bit in the software control register
is asserted. The output value depends on the DAC coding that is
being used, either binary or twos complement. The default
register value is 0.
Table 10. Control Register
MSB
LSB
DB23
DB22
DB21
DB20
DB19 to DB11
DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
R/W
Register address
Control register data
R/W
0
1
0
Reserved
0000
SDODIS
BIN/2sC
DACTRI
OPGND
RBUF
Reserved
Table 11. Control Register Functions
Bit Name
Description
Reserved
These bits are reserved and should be programmed to zero.
RBUF
Output amplifier configuration control.
0: the internal amplifier, A1, is powered up and Resistors RFB and R1 are connected in series as shown in Figure 52. This allows
an external amplifier to be connected in a gain of two configuration. See the AD5780 Features section for further details.
1: (default) the internal amplifier, A1, is powered down and Resistors RFB and R1 are connected in parallel, as shown in Figure 51,
so that the resistance between the RFB and INV pins is 3.4 k, equal to the resistance of the DAC. This allows the RFB and INV
pins to be used for input bias current compensation for an external unity-gain amplifier. See the AD5780 Features section for
further details.
OPGND
Output ground clamp control.
0: the DAC output clamp to ground is removed, and the DAC is placed in normal mode.
1: (default) the DAC output is clamped to ground through a ~6 k resistance, and the DAC is placed in tristate mode.
Resetting the part puts the DAC in OPGND mode, where the output ground clamp is enabled and the DAC is tristated. Setting
the OPGND bit to 1 in the control register overrules any write to the DACTRI bit
DACTRI
DAC tristate control.
0: the DAC is in normal operating mode.
1: (default) the DAC is in tristate mode.
BIN/2sC
DAC register coding selection.
0: (default) the DAC register uses twos complement coding.
1: the DAC register uses offset binary coding.
SDODIS
SDO pin enable/disable control.
0: (default) the SDO pin is enabled.
1: the SDO pin is disabled (tristate).
R/W
Read/write select bit.
0: AD5780 is addressed for a write operation.
1: AD5780 is addressed for a read operation.
Table 12. Clearcode Register
MSB
LSB
DB23
DB22
DB21
DB20
DB19 to DB2
DB1
DB0
R/W
Register address
Clearcode register data
R/W
0
1
18 bits of data
X1
1
X is don’t care.
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