參數資料
型號: AD5765CSUZ
廠商: Analog Devices Inc
文件頁數: 17/28頁
文件大?。?/td> 0K
描述: IC DAC 16BIT QUAD 5V 1LSB 32TQFP
產品培訓模塊: Data Converter Fundamentals
DAC Architectures
產品變化通告: AD5763/65 Metal Layer Edit Change 08/Sept/2009
設計資源: High Accuracy, Bipolar Voltage Output Digital-to-Analog Conversion Using AD5765 (CN0073)
標準包裝: 1
設置時間: 8µs
位數: 16
數據接口: 串行
轉換器數目: 4
電壓電源: 雙 ±
功率耗散(最大): 76mW
工作溫度: -40°C ~ 105°C
安裝類型: 表面貼裝
封裝/外殼: 32-TQFP
供應商設備封裝: 32-TQFP(7x7)
包裝: 托盤
輸出數目和類型: 4 電壓,雙極
采樣率(每秒): *
產品目錄頁面: 784 (CN2011-ZH PDF)
AD5765
Data Sheet
Rev. C | Page 24 of 28
POWER-ON STATUS
The AD5765 has multiple power supply and digital input pins.
It is important to consider the sequence in which the pins are
powered up to ensure that the AD5765 powers on in the
required state. The outputs power on either clamped to
AGNDx, driving 0 V, or driving negative full-scale output
(4.096 V), depending on how the BIN/2sCOMP, CLR, and
LDAC pins are configured during power-up.
The CLR pin, if connected to DGND, causes the DAC registers
to be loaded with 0x0000 and the outputs to be updated;
consequently, the outputs are loaded with 0 V if BIN/2sCOMP
is connected to DGND or with negative full-scale (4.096 V) if
BIN/2sCOMP is connected to DVCC, corresponding respectively
to the twos complement and binary voltages for the digital code
0x0000. During power-up, the state of the LDAC pin has an
identical effect to that of the CLR pin. If both the CLR and
LDAC pins are connected to DVCCduring power-up, the
outputs power on clamped to AGNDx and remain so until a
valid write is made to the device. Table 20 outlines the possible
output power-on states.
Table 20. Output Power-On States
BIN/2sCOMP
CLR
LDAC
VOUT at Power-On
DGND
0 V
DGND
DVCC
0 V
DGND
DVCC
DGND
0 V
DGND
DVCC
Clamped to AGNDx
DVCC
DGND
4.096 V
DVCC
DGND
DVCC
4.096 V
DVCC
DGND
4.096 V
DVCC
Clamped to AGNDx
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