參數(shù)資料
型號: AD5764ASU
廠商: ANALOG DEVICES INC
元件分類: DAC
英文描述: Complete, Quad, 16-Bit, High Accuracy, Serial Input, Bipolar Voltage Output DAC
中文描述: SERIAL INPUT LOADING, 8 us SETTLING TIME, 16-BIT DAC, PQFP32
封裝: MO-026-ABA, TQFP-32
文件頁數(shù): 18/27頁
文件大?。?/td> 251K
代理商: AD5764ASU
AD5764
Preliminary Technical Data
Rev. PrC 21-Oct-04| Page 18 of 28
V
OUT
DAC
REGISTER
INTERFACE
LOGIC
OUTPUT
I/V AMPLIFIER
LDAC
SDO
SDIN
16-BIT
DAC
V
REFIN
SYNC
INPUT
REGISTER
SCLK
Figure 9. Simplified Serial Interface showing input loading
circuitry for one DAC Channel
TRANSFER FUNCTION
Table Shows the ideal input code to output voltage relationship
for the AD5764 for both straight binary and twos complement
data coding.
Digital Input
Analog Output
V
OUT
+2 V
REF
x (32767/32768)
+2 V
REF
x (1/32768)
Straight Binary Data Coding
MSB
1111
1000
1000
0111
0000
LSB
1111
0000
0000
1111
0000
1111
0000
0000
1111
0000
1111
0001
0000
1111
0000
0 V
-2 V
REF
x (1/32768)
-2 V
REF
x (32767/32768)
Twos Complement Data Coding
MSB
0111
1111
0000
0000
0000
0000
1111
1111
1000
0000
LSB
V
OUT
1111
0000
0000
1111
0000
1111
0001
0000
1111
0000
+2 V
REF
x (32767/32768)
+2 V
REF
x (1/32768)
0 V
-2 V
REF
x (1/32768)
-2 V
REF
x (32767/32768)
The output voltage expression is given by
×
+
×
=
65536
4
2
D
V
V
V
REFIN
REFIN
OUT
where:
D is the decimal equivalent of the code loaded to the DAC.
V
REFIN
is the reference voltage applied at the REFIN pin.
ASYNCHRONOUS CLEAR (CLR)
CLR is an active low, level sensitive clear that allows the outputs
to be cleared to either 0 V (straight binary coding) or negative
full scale (twos complement coding). It is necessary to maintain
CLR low for a minimum amount of time (refer to Figure 3) for
the operation to complete. When the CLR signal is returned
high, the output remains at the cleared value until a new value is
programmed. The CLR signal has priority over LDAC and
SYNC. A clear can also be initiated through software by writing
the command 0x04XXXX to the AD5764.
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