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參數(shù)資料
| 型號： | AD5764ASU |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | DAC |
| 英文描述： | Complete, Quad, 16-Bit, High Accuracy, Serial Input, Bipolar Voltage Output DAC |
| 中文描述： | SERIAL INPUT LOADING, 8 us SETTLING TIME, 16-BIT DAC, PQFP32 |
| 封裝： | MO-026-ABA, TQFP-32 |
| 文件頁數(shù)： | 11/27頁 |
| 文件大?。?/td> | 251K |
| 代理商： | AD5764ASU |
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Preliminary Technical Data
AD5764
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Rev. PrC 21-Oct-04| Page 11 of 28
AD5764
TOP VIEW
(Not to Scale)
SYNC
SCLK
SDIN
SDO
CLR
LDAC
D1
D0
AGNDA
VOUTA
VOUTB
AGNDB
AGNDC
VOUTC
VOUTD
AGNDD
R
R
D
D
C
A
D
P
I
A
S
B
A
D
A
S
T
R
R
R
R
1
32
25
9
16
8
24
17
PIN 1
0
Figure 6. 32-Lead TQFP Pin Configuration Diagram
Table 5. Pin Function Descriptions
Pin No.
1
Mnemonic
SYNC
Function
Active Low Input. This is the frame synchronization signal for the serial interface.
While SYNC is low, data is transferred in on the falling edge of SCLK.
Serial Clock Input. Data is clocked into the shift register on the falling edge of SCLK.
This operates at clock speeds up to 30 MHz.
Serial Data Input. Data must be valid on the falling edge of SCLK.
Serial Data Output. Used to clock data from the serial register in daisy-chain or
readback mode.
Active Low Input. Asserting this pin sets the DAC registers to 0x0000.
Load DAC. Logic input. This is used to update the DAC registers and consequently
the analog output. When tied permanently low, the addressed DAC register is
updated on the 24
th
clock of the serial register write. If LDAC is held high during the
write cycle, the DAC input register is updated but the output is held off until the
falling edge of LDAC. In this mode, all analog outputs can be updated
simultaneously on the falling edge of LDAC.
D0 and D1 form a digital I/O port. The user can configure these pins as inputs or
outputs that are configurable and readable over the serial interface. When
configured as inputs, these pins have weak internal pull-ups to DV
CC
.
Reset Logic Output. This is the output from the on-chip voltage monitor used in the
reset circuit. If desired, it may be used to control other system components.
Reset Logic Input. This input allows external access to the internal reset logic.
Applying a Logic 0 to this input resets the DAC output to 0 V. In normal operation,
RSTIN should be tied to Logic 1.
Digital GND Pin.
Digital Supply Pin. Voltage ranges from 2.7 V to 5.5 V. When programmed as
outputs, D0 and D1 are referenced to DV
CC
.
Positive Analog Supply Pins. Voltage ranges from 11.4 V to 15.75 V.
Ground Reference Point for Analog Circuitry.
Negative Analog Supply Pins. Voltage ranges from –11.4 V to –15.75 V.
This pin us used in association with an external resistor to AGND to program the
short-circuit current of the output amplifiers.
Ground Reference Pin for DAC D Output amplifier.
2
SCLK
13
3
4
SDIN
13
SDO
5
6
CLR
13
LDAC
7, 8
D0, D1
9
RSTOUT
10
RSTIN
11
12
DGND
DV
CC
13, 31
14
15, 30
16
AV
DD
PGND
AV
SS
ISCC
17
AGNDD
13
Internal pull-up device on this logic input. Therefore, it can be left floating and will default to a logic high condition.
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