參數(shù)資料
型號： AD5762RCSUZ-REEL7
廠商： ANALOG DEVICES INC
元件分類： DAC
英文描述： Complete Dual, 16-Bit, High Accuracy, Serial Input, Bipolar Voltage Output DACs
中文描述： SERIAL INPUT LOADING, 8 us SETTLING TIME, 16-BIT DAC, PQFP32
封裝： ROHS COMPLIANT, PLASTIC, MS-026ABA, TQFP-32
文件頁數(shù)： 7/33頁
文件大?。?/td> 507K
代理商： AD5762RCSUZ-REEL7
Preliminary Technical Data
AD5762R
TIMING CHARACTERISTICS
AV
DD
= 11.4 V to 16.5 V, AV
SS
= 11.4 V to 16.5 V, AGND = DGND = REFGND = PGND = 0 V; REFA, REFB= 5 V external;
DV
CC
= 2.7 V to 5.25 V, R
LOAD
= 10 k, C
L
= 200 pF. All specifications T
MIN
to T
MAX
, unless otherwise noted.
Table 3.
Parameter
1, 2, 3
Limit at T
MIN
, T
MAX
Unit
t
1
33
ns min
t
2
13
ns min
t
3
13
ns min
t
4
13
ns min
t
54
13
ns min
t
6
40
ns min
t
7
2
ns min
t
8
5
ns min
t
9
1.4
μs min
400
ns min
t
10
10
ns min
t
11
500
ns max
t
12
10
μs max
t
13
10
ns min
t
14
2
μs max
t
155, 6
25
ns max
t
16
13
ns min
t
17
2
μs min
t
18
170
ns min
1
Guaranteed by design and characterization; not production tested.
2
All input signals are specified with t
r
= t
f
= 5 ns (10% to 90% of DV
CC
) and timed from a voltage level of 1.2 V.
3
See Figure 2, Figure 3, and Figure 4.
4
Standalone mode only.
5
Measured with the load circuit of Figure 5.
6
Daisy-chain mode only.
Rev. PrA | Page 7 of 33
Description
SCLK cycle time
SCLK high time
SCLK low time
SYNC falling edge to SCLK falling edge setup time
24
th
SCLK falling edge to SYNC rising edge
Minimum SYNC high time
Data setup time
Data hold time
SYNC rising edge to LDAC falling edge (all DACs updated)
SYNC rising edge to LDAC falling edge (single DAC updated)
LDAC pulse width low
LDAC falling edge to DAC output response time
DAC output settling time
CLR pulse width low
CLR pulse activation time
SCLK rising edge to SDO valid
SYNC rising edge to SCLK falling edge
SYNC rising edge to DAC output response time (LDAC = 0)
LDAC falling edge to SYNC rising edge
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