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參數(shù)資料
| 型號： | AD5762RCSUZ-REEL7 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | DAC |
| 英文描述： | Complete Dual, 16-Bit, High Accuracy, Serial Input, Bipolar Voltage Output DACs |
| 中文描述： | SERIAL INPUT LOADING, 8 us SETTLING TIME, 16-BIT DAC, PQFP32 |
| 封裝： | ROHS COMPLIANT, PLASTIC, MS-026ABA, TQFP-32 |
| 文件頁數(shù)： | 31/33頁 |
| 文件大?。?/td> | 507K |
| 代理商： | AD5762RCSUZ-REEL7 |
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Preliminary Technical Data
AD5762R
When data is being transmitted to the AD5762R, the SYNC line
(PC7) is taken low and data is transmitted MSB first. Data
appearing on the MOSI output is valid on the falling edge of
SCK. Eight falling clock edges occur in the transmit cycle, so, in
order to load the required 24-bit word, PC7 is not brought high
until the third 8-bit word has been transferred to the DACs
input shift register.
Rev. PrA | Page 31 of 33
MC68HC11
1
1
ADDITIONAL PINS OMITTED FOR CLARITY
Figure 44. AD5762R to MC68HC11 Interface
AD5762R
1
SDO
MISO
SDIN
MOSI
SCLK
SCK
SYNC
PC7
0
LDAC is controlled by the PC6 port output. The DAC can be
updated after each 3-byte transfer by bringing LDAC low. This
example does not show other serial lines for the DAC. For
example, if CLR were used, it could be controlled by port
output PC5.
AD5762R to 8XC51 Interface
The AD5762R requires a clock synchronized to the serial data.
For this reason, the 8XC51 must be operated in Mode 0. In this
mode, serial data enters and exits through RXD, and a shift
clock is output on TXD.
P3.3 and P3.4 are bit programmable pins on the serial port and
are used to drive SYNC and LDAC, respectively. The 8CX51
provides the LSB of its SBUF register as the first bit in the data
stream. The user must ensure that the data in the SBUF register
is arranged correctly, because the DAC expects MSB first. When
data is to be transmitted to the DAC, P3.3 is taken low. Data on
RXD is clocked out of the microcontroller on the rising edge of
TXD and is valid on the falling edge. As a result, no glue logic is
required between this DAC and the microcontroller interface.
8XC51
1
1
ADDITIONAL PINS OMITTED FOR CLARITY
AD5762R
1
SCLK
TxD
SDIN
RxD
SYNC
P3.3
LDAC
P3.4
0
Figure 45. AD5762R to 8XC51 Interface
The 8XC51 transmits data in 8-bit bytes with only eight falling
clock edges occurring in the transmit cycle. Because the DAC
expects a 24-bit word, SYNC (P3.3) must be left low after the
first eight bits are transferred. After the third byte has been
transferred, the P3.3 line is taken high. The DAC can be
updated using LDAC via P3.4 of the 8XC51.
AD5762R to ADSP2101/ADSP2103 Interface
An interface between the AD5762R and the ADSP2101/
ADSP2103 is shown in Figure 46. The ADSP2101/ ADSP2103
should be set up to operate in the SPORT transmit alternate
framing mode. The ADSP2101/ADSP2103 are programmed
through the SPORT control register and should be configured
as follows: internal clock operation, active low framing, and 24-
bit word length.
Transmission is initiated by writing a word to the TX register
after the SPORT has been enabled. As the data is clocked out of
the DSP on the rising edge of SCLK, no glue logic is required to
interface the DSP to the DAC. In the interface shown, the DAC
output is updated using the LDAC pin via the DSP. Alterna-
tively, the LDAC input could be tied permanently low, and then
the update takes place automatically when TFS is taken high.
SCLK
SDIN
SYNC
DT
SCLK
RFS
ADSP2101/
ADSP2103
1
1
ADDITIONAL PINS OMITTED FOR CLARITY
SDO
DR
TFS
LDAC
FO
AD5762R
1
0
Figure 46. AD5762R to ADSP2101/ADSP2103 Interface
AD5762R to PIC16C6x/7x Interface
The PIC16C6x/7x synchronous serial port (SSP) is configured
as an SPI master with the clock polarity bit set to 0. This is done
by writing to the synchronous serial port control register
(SSPCON). See the
PIC16/17 Microcontroller User Manual
. In
this example, I/O port RA1 is being used to pulse SYNC and
enable the serial port of the AD5762R. This microcontroller
transfers only eight bits of data during each serial transfer
operation; therefore, three consecutive write operations are
needed. Figure 47 shows the connection diagram.
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| AD5763 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Complete Dual, 16-Bit, High Accuracy, Serial Input, ±5V DACs |
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| AD5763CSUZ | 功能描述:DAC 16BIT DUAL 5V 2LSB 32-TQFP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器 系列:- 標(biāo)準(zhǔn)包裝:1 系列:- 設(shè)置時間:4.5µs 位數(shù):12 數(shù)據(jù)接口:串行，SPI? 轉(zhuǎn)換器數(shù)目:1 電壓電源:單電源 功率耗散（最大）:- 工作溫度:-40°C ~ 125°C 安裝類型:表面貼裝 封裝/外殼:8-SOIC（0.154"，3.90mm 寬） 供應(yīng)商設(shè)備封裝:8-SOICN 包裝:剪切帶 (CT) 輸出數(shù)目和類型:1 電壓，單極；1 電壓，雙極 采樣率（每秒）:* 其它名稱:MCP4921T-E/SNCTMCP4921T-E/SNRCTMCP4921T-E/SNRCT-ND |
| AD5763CSUZ-REEL7 | 功能描述:DAC 16BIT DUAL 5V 2LSB 32-TQFP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器 系列:- 產(chǎn)品培訓(xùn)模塊:Data Converter Fundamentals DAC Architectures 標(biāo)準(zhǔn)包裝:750 系列:- 設(shè)置時間:7µs 位數(shù):16 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:1 電壓電源:雙 ± 功率耗散（最大）:100mW 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:28-LCC（J 形引線） 供應(yīng)商設(shè)備封裝:28-PLCC（11.51x11.51） 包裝:帶卷 (TR) 輸出數(shù)目和類型:1 電壓，單極；1 電壓，雙極 采樣率（每秒）:143k |
| AD5763CSUZ-TR | 制造商:Analog Devices 功能描述:16BIT +/-5V DUAL 1LSB - Tape and Reel |
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