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參數(shù)資料
| 型號(hào)： | AD5744CSU |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | DAC |
| 英文描述： | Complete, Quad, 14/16-Bit, High Accuracy, Serial Input, Bipolar Voltage Output DAC |
| 中文描述： | SERIAL INPUT LOADING, 8 us SETTLING TIME, 14-BIT DAC, PQFP32 |
| 封裝： | MO-026-ABA, TQFP-32 |
| 文件頁(yè)數(shù)： | 7/27頁(yè) |
| 文件大小： | 243K |
| 代理商： | AD5744CSU |
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Preliminary Technical Data
TIMING CHARACTERISTICS
AV
DD
= +11.4 V to +16.5 V, AV
SS
= 11.4 V to 16.5 V, AGND = DGND = REFGND = PGND = 0 V; REFAB = REFCD= 5 V Ext;
DV
CC
= 2.7 V to 5.5 V, R
LOAD
= 10 k, C
L
= 200 pF. All specifications T
MIN
to T
MAX
, unless otherwise noted.
Table 3.
Parameter
7,8,9
Limit at T
MIN
, T
MAX
Unit
t
1
33
ns min
t
2
13
ns min
t
3
13
ns min
t
4
13
ns min
t
5
10
13
ns min
t
6
40
ns min
t
7
5
ns min
t
8
0
ns min
t
9
20
ns min
t
10
20
ns min
t
11
5
ns min
t
12
10
μs max
t
13
20
ns min
t
14
12
μs max
t
1511,12
20
ns max
t
1612
8
ns min
t
1712
20
ns min
Rev. PrA 15-Nov-04| Page 7 of 27
Description
SCLK cycle time
SCLK high time
SCLK low time
SYNC falling edge to SCLK falling edge setup time
24
th
SCLK falling edge to SYNC rising edge
Minimum SYNC high time
Data setup time
Data hold time
SYNC rising edge to LDAC falling edge
LDAC pulse width low
LDAC falling edge to DAC output response time
DAC output settling time
CLR pulse width low
CLR pulse activation time
SCLK rising edge to SDO valid
SCLK falling edge to SYNC rising edge
SYNC rising edge to LDAC falling edge
7
Guaranteed by design and characterization. Not production tested.
8
All input signals are specified with t
r
= t
f
= 5 ns (10% to 90% of DV
CC
) and timed from a voltage level of 1.2 V.
9
See Figure 2, Figure 3, and Figure 4.
10
Stand-alone mode only.
11
Measured with the load circuit of Figure 5.
12
Daisy-chain mode only.
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