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參數(shù)資料
| 型號(hào)： | AD5726YRWZ-REEL7 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類(lèi)： | DAC |
| 英文描述： | Quad 12-Bit Serial Input Unipolar/Bipolar Voltage Output DAC |
| 中文描述： | QUAD, SERIAL INPUT LOADING, 13 us SETTLING TIME, 12-BIT DAC, PDSO16 |
| 封裝： | ROHS COMPLIANT, MO-013AA, SOIC-16 |
| 文件頁(yè)數(shù)： | 6/20頁(yè) |
| 文件大?。?/td> | 405K |
| 代理商： | AD5726YRWZ-REEL7 |
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AD5726
TIMING CHARACTERISTICS
AV
DD
= +15 V/+5 V, AV
SS
= 15 V/5 V/0 V, GND = 0 V; V
REFP
= +10 V/+2.5 V; V
REFN
= 10 V/2.5 V/0 V, V
L
= 5 V, R
LOAD
= 2 kΩ,
C
L
= 200 pF. All specifications T
MIN
to T
MAX
, unless otherwise noted.
1, 2
Rev. 0 | Page 6 of 20
Table 5.
Parameter
t
DS
t
DH
t
CH
t
CL
t
CSS
t
CSH
t
LD1
t
LD2
t
LDW
t
CLRW
1
Guaranteed by design and characterization, not production tested.
2
All input control signals are specified with tr = tf = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V.
Limit at T
MIN
, T
MAX
5
5
13
13
13
13
20
20
20
20
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Description
Data setup time.
Data hold time.
Clock pulse width high.
Clock pulse width low.
Select time.
Deselect delay.
Load disable time.
Load delay.
Load pulse width.
Clear pulse width.
CS
SDIN
SCLK
LDAC
t
CSS
t
LD1
t
CSH
t
LD2
A1
A0
X
X
D11
D10
D9
D8
D4
D3
D2
D1
D0
0
Figure 2. Data Load Sequence
SDIN
SCLK
V
OUT
CS
LDAC
t
DS
t
CL
t
CH
t
CSH
t
LD2
t
LDW
t
S
t
DH
±1LSB
0
Figure 3. Data Load Timing
CLRSEL
V
OUT
CLR
t
CLRW
t
S
±1LSB
0
Figure 4. Clear Timing
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| AD572AD | 制造商:Analog Devices 功能描述: 制造商:Rochester Electronics LLC 功能描述:12-BIT ADC IC - Bulk 制造商:AD 功能描述:_ |
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