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參數(shù)資料
| 型號： | AD568SQ |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | DAC |
| 英文描述： | 12-Bit Ultrahigh Speed Monolithic D/A Converter |
| 中文描述： | PARALLEL, WORD INPUT LOADING, 0.05 us SETTLING TIME, 12-BIT DAC, CDIP24 |
| 封裝： | 0.300 INCH, HERMETIC SEALED, CERDIP-24 |
| 文件頁數(shù)： | 4/14頁 |
| 文件大小： | 541K |
| 代理商： | AD568SQ |
AD568
REV. A
–4–
their glitch impulse. It is specified as the net area of the glitch in
nV-sec or pA-sec.
COMPLIANCE VOLTAGE: The range of allowable voltage at
the output of a current-output DAC which will not degrade the
accuracy of the output current.
SETTLING TIME: The time required for the output to reach
and remain within a specified error band about its final value,
measured from the digital input transition.
TIME – ns
0.8
0
250
50
O
100
150
200
0.6
0.4
Figure 2. Glitch Impulse
Connecting the AD568
UNBUFFERED VOLTAGE OUTPUT
Unipolar Configuration
Figure 3 shows the AD568 configured to provide a unipolar 0 to
+1.024 V output range. In this mode, the bipolar offset termi-
nal, Pin 21, should be grounded if not used for offset trimming.
The nominal output impedance of the AD568 with Pin 19
grounded has been trimmed to 100
,
±
1%. Other output im-
pedances can be generated with an external resistor, R
EXT
, be-
tween Pins 19 and 20. An R
EXT
equalling 300
will yield a
total output resistance of 75
, while an R
EXT
of 100
will pro-
vide 50
of output resistance. Note that since the full-scale
output current of the DAC remains 10.24 mA, changing the
load impedance changes the unbuffered output voltage accord-
ingly. Settling time and full-scale range characteristics for these
load impedances are provided in the specifications table.
Bipolar Configuration
Figure 4 shows the connection scheme used to provide a bipolar
output voltage range of 1.024 V. The bipolar offset (–0.512 V)
occurs when all bits are OFF (00 . . . 00), bipolar zero (0 V) oc-
curs when the MSB is ON with all other bits OFF (10 . . . 00),
and full-scale minus 1 LSB (0.51175 V) is generated when all
bits are ON (11 . . . 11). Figure 5 shows an optional bipolar
mode with a 2.048 V range. The scale factor in this mode will
not be as accurate as the configuration shown in Figure 4, be-
cause the laser-trimmed resistor R
L
is not used.
13
16
15
14
24
23
22
21
20
19
18
17
12
11
10
9
8
1
2
3
4
7
6
5
AD568
+15V
REFCOM
–15V
I
BPO
I
OUT
R
L
ACOM
LCOM
SPAN
SPAN
THCOM
VTH
DIGITAL
INPUTS
0.2μF
0.1μF
0.1μF
0.1μF
–15V
+15V
ANALOG
GND PLANE
DIGITAL
GND PLANE
DIGITAL
SUPPLY
GROUND
100pF
R
TH
1k
+5V
ANALOG
OUTPUT
R
(OPTIONAL)
FERRITE BEADS
STACKPOLE 57-1392
OR
AMIDON FB-43B-101
OR EQUIVALENT
NC
NC
ANALOG
SUPPLY
GROUND
Figure 3. Unipolar Output Unbuffered 0 V to +1.024 V
13
16
15
14
24
23
22
21
20
19
18
17
12
11
10
9
8
1
2
3
4
7
6
5
AD568
+15V
REFCOM
–15V
I
BPO
I
OUT
R
L
ACOM
LCOM
SPAN
SPAN
THCOM
VTH
DIGITAL
INPUTS
0.2μF
0.1μF
0.1μF
0.1μF
–15V
+15V
ANALOG
GND PLANE
DIGITAL
GND PLANE
DIGITAL
SUPPLY
GROUND
100pF
+5V
ANALOG
OUTPUT
ANALOG
SUPPLY
GROUND
Figure 4. Bipolar Output Unbuffered
±
0.512 V
Figure 4 also demonstrates how the internal span resistor may
be used to bias the V
TH
pin (Pin 13) from a 5 V supply. This
eliminates the requirement for an external R
TH
in applications
that do not require the precision span resistor.
BIPOLAR ZERO ERROR: The deviation of the analog output
from the ideal half-scale output of 0 V (or 0 mA) for bipolar
mode when only the MSB is on (100 . . .00) is called bipolar
zero error.
GAIN ERROR: The difference between the ideal and actual
output span of FS –1 LSB, expressed in % of FS, or LSB, when
all bits are on.
GLITCH IMPULSE: Asymmetrical switching times in a DAC
give rise to undesired output transients which are quantified by
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