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參數(shù)資料
| 型號(hào)： | AD5663ARMZ |
| 廠(chǎng)商： | Analog Devices Inc |
| 文件頁(yè)數(shù)： | 9/24頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC NANO 16BIT DUAL 10-MSOP |
| 產(chǎn)品培訓(xùn)模塊： | Data Converter Fundamentals DAC Architectures |
| 標(biāo)準(zhǔn)包裝： | 50 |
| 系列： | nanoDAC™ |
| 設(shè)置時(shí)間： | 4µs |
| 位數(shù)： | 16 |
| 數(shù)據(jù)接口： | 串行 |
| 轉(zhuǎn)換器數(shù)目： | 2 |
| 電壓電源： | 單電源 |
| 功率耗散（最大）： | 2.5mW |
| 工作溫度： | -40°C ~ 105°C |
| 安裝類(lèi)型： | 表面貼裝 |
| 封裝/外殼： | 10-TFSOP，10-MSOP（0.118"，3.00mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 10-MSOP |
| 包裝： | 管件 |
| 輸出數(shù)目和類(lèi)型： | 2 電壓，單極；2 電壓，雙極 |
| 采樣率（每秒）： | 220k |
| 產(chǎn)品目錄頁(yè)面： | 783 (CN2011-ZH PDF) |
| 配用： | EVAL-AD5663REBZ-ND - BOARD EVAL FOR AD5663 |
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AD5663
Rev. 0 | Page 17 of 24
Synchronous LDAC:
The DAC registers are updated after new
data is read in on the falling edge of the 24th SCLK pulse.
LDAC can be permanently low or pulsed, as shown in Figure 2.
Asynchronous LDAC:
The outputs are not updated at the same
time that the input registers are written to. When LDAC goes
low, the DAC registers are updated with the contents of the
input register.
The LDAC register gives the user full flexibility and control
over the hardware LDAC pin. This register allows the user to
select which combination of channels to simultaneously update
when the hardware LDAC pin is executed. Setting the LDAC bit
register to 0 for a DAC channel means that the update of this
channel is controlled by the LDAC pin. If this bit is set to 1, this
channel synchronously updates; that is, the DAC register is
updated after new data is read in, regardless of the state of the
LDAC pin. It effectively sees the LDAC pin as being pulled low.
See Table 13 for the LDAC register mode of operation.
This flexibility is useful in applications where the user wants to
simultaneously update select channels while the rest of the
channels are synchronously updating
Writing to the DAC using Command 110 loads the 2-bit LDAC
register [DB1:DB0]. The default for each channel is 0; that is,
the LDAC pin works normally. Setting the bits to 1 means the
DAC register is updated regardless of the state of the LDAC pin.
See Table 14 for contents of the input shift register during the
LDAC register setup command.
Table 13. LDAC Register Mode of Operation
LDAC Bits
(DB1 to DB0)
LDAC Pin
LDAC Operation
0
1/0
Determined by LDAC pin
1
x = don’t care
The DAC registers are updated
after new data is read in on the
falling edge of the 24th SCLK
pulse
Table 14. 24-Bit Input Shift Register Contents for LDAC Register Setup Command
MSB
LSB
DB23 to DB22
DB21
DB20
DB19
DB18
DB17
DB16
DB15 to DB2
DB1
DB0
x
1
0
x
DAC B
DAC A
Don’t care
Command bits (C2 to C0)
Address bits (A3 to A0);
Don’t care
Set DAC to 0 or 1 for required mode of
operation
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