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參數(shù)資料
| 型號(hào)： | AD565ATQ |
| 英文描述： | 12-Bit Digital-to-Analog Converter |
| 中文描述： | 12位數(shù)字到模擬轉(zhuǎn)換器 |
| 文件頁(yè)數(shù)： | 6/11頁(yè) |
| 文件大小： | 152K |
| 代理商： | AD565ATQ |
AD565A/AD566A
REV. D
–6–
ABSOLUTE MAXIMUM RATINGS
V
CC
to Power Ground . . . . . . . . . . . . . . . . . . . . . 0 V to +18 V
V
EE
to Power Ground (AD565A) . . . . . . . . . . . . 0 V to –18 V
Voltage on DAC Output (Pin 9) . . . . . . . . . . . . –3 V to +12 V
Digital Inputs (Pins 13 to 24) to
Power Ground . . . . . . . . . . . . . . . . . . . . . . –1.0 V to +7.0 V
REF IN to Reference Ground . . . . . . . . . . . . . . . . . . . .
±
12 V
Bipolar Offset to Reference Ground . . . . . . . . . . . . . . .
±
12 V
10 V Span R to Reference Ground . . . . . . . . . . . . . . . .
±
12 V
20 V Span R to Reference Ground . . . . . . . . . . . . . . . .
±
24 V
REF OUT (AD565A) . . . . . Indefinite Short to Power Ground
Momentary Short to V
CC
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . 1000 mW
AD565A ORDERING GUIDE
Max Gain
T.C. (ppm
of F.S./ C)
Linearity
Error Max Package
@ +25 C
Temperature
Range
Model
1
Options
2
AD565AJD
AD565AJR
AD565AKD 20
AD565ASD
AD565ATD
50
50
0
°
C to +70
°
C
0
°
C to +70
°
C
0
°
C to +70
°
C
–55
°
C to +125
°
C
–55
°
C to +125
°
C
±
1/2 LSB
±
1/2 LSB
±
1/4 LSB
±
1/2 LSB
±
1/4 LSB
Ceramic (D-24)
SOIC (R-28)
Ceramic (D-24)
Ceramic (D-24)
Ceramic (D-24)
30
15
NOTES
1
For details on grade and package offerings screened in accordance with MIL-
STD-883, refer to the Analog Devices Military Products Databook or current/
883B data sheet.
2
D = Ceramic DIP, R = SOIC.
AD566A ORDERING GUIDE
Max Gain
T.C. (ppm
of F.S./ C)
Linearity
Error Max Package
@ +25 C
Temperature
Range
Model
1
Option
2
AD566AJD
AD566AKD 3
AD566ASD
AD566ATD
10
0
°
C to +70
°
C
0
°
C to +70
°
C
–55
°
C to +125
°
C
–55
°
C to +125
°
C
±
1/2 LSB
±
1/4 LSB
±
1/2 LSB
±
1/4 LSB
Ceramic (D-24)
Ceramic (D-24)
Ceramic (D-24)
Ceramic (D-24)
10
3
NOTES
1
For details on grade and package offerings screened in accordance with MIL-
STD-883, refer to the Analog Devices Military Products Databook or current/
883B data sheet.
2
D = Ceramic DIP.
GROUNDING RULES
The AD565A and AD566A bring out separate reference and
power grounds to allow optimum connections for low noise and
high-speed performance. These grounds should be tied together
at one point, usually the device power ground. The separate
ground returns are provided to minimize current flow in
low-level signal paths. In this way, logic return currents are not
summed into the same return path with analog signals.
CONNECTING THE AD565A FOR BUFFERED VOLTAGE
OUTPUT
The standard current-to-voltage conversion connections using
an operational amplifier are shown here with the preferred
trimming techniques. If a low offset operational amplifier
(AD510L, AD517L, AD741L, AD301AL, AD OP07) is used,
excellent performance can be obtained in many situations with-
out trimming (an op amp with less than 0.5 mV max offset
voltage should be used to keep offset errors below 1/2 LSB). If
a 50
fixed resistor is substituted for the 100
trimmer, uni-
polar zero will typically be within
±
1/2 LSB (plus op amp off-
set), and full-scale accuracy will be within 0.1% (0.25% max).
Substituting a 50
resistor for the 100
bipolar offset trimmer
will give a bipolar zero error typically within
±
2 LSB (0.05%).
The AD509 is recommended for buffered voltage-output appli-
cations which require a settling time to
±
1/2 LSB of one micro-
second. The feedback capacitor is shown with the optimum
value for each application; this capacitor is required to compen-
sate for the 25 picofarad DAC output capacitance.
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